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In this paper, a new flip-flop called Double-edge triggered Feedback Flip-Flop (DFFF) is proposed. The dynamic power consumption of DFFF is reduced by avoiding unnecessary internal node transition. The subthreshold current in the flip-flops is very low compared to other structures. Reducing the number of transistor in the stack and increasing the number of(More)
This study concerns the existence of positive solutions to classes of boundary value problems of the form where ∆ denote the Laplacian operator, Ω is a smooth bounded domain in R N (N ≥ 2) with ∂Ω of class C 2 , and connected, and g(x, 0) < 0 for some x ∈ Ω (semipositone problems). By using the method of sub-super solutions we prove the existence of(More)
A low power pulse triggered flipflop (P-FF) design is done by the pulse generation control logic, an AND function, is removed from the critical path to facilitate a faster discharge operation. A simple two-transistor AND gate design is used to reduce the circuit complexity. A conditional pulse enhancement technique is devised to speed up the discharge along(More)
In this paper, a new flip flop called clock gated static pulsed flip-flop (CGSPFF) is proposed. The dynamic power consumption in CGSPFF is reduced by avoiding unnecessary input pulse transitions with clock gating. Two transistors in the main block of the flip-flop are eliminated to achieve low leakage power as well. Using the new clock pulse generator leads(More)
In this paper a new low power flip-flop called Double-edge triggered Modified Hybrid Latch Flip-Flop (DMHLFF) has been proposed and compared to previous flip-flops. DMHLFF is a low power, low area, and fast flip-flop. Power consumption is reduced by avoiding unnecessary internal node transition. Power consumption in clock tree is also reduced by decreasing(More)
An optimization approach for design of domino logic circuit using genetic algorithm is proposed in this paper. Simulation-based genetic algorithm is used to design of domino logic circuit to achieve a high accurate result. By the given noise margin, delay, leakage power and active power, the fitness function is defined and the genetic algorithm is used to(More)
This paper enumerates high speed design of RS & D-flip-flop using AlGaAs/GaAs MODFET. The proposed Flip Flop is having less number of transistors than existing designs. Simulation results show lowest average power and least delay than existing designs. This Flip-Flop having less number of transistors. It can be efficiently used in VLSI ICs. In the(More)