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- S. H. Rasouli, A. Amirabadi, A. Seyedi, Ali Afzali-Kusha
- ASP-DAC
- 2006

In this paper, a new flip-flop called Double-edge triggered Feedback Flip-Flop (DFFF) is proposed. The dynamic power consumption of DFFF is reduced by avoiding unnecessary internal node transition. The subthreshold current in the flip-flops is very low compared to other structures. Reducing the number of transistor in the stack and increasing the number of… (More)

- A. S. Seyedi, S. H. Rasouli, A. Amirabadi, Ali Afzali-Kusha
- IEEE Computer Society Annual Symposium on…
- 2006

In this paper, a new flip flop called clock gated static pulsed flip-flop (CGSPFF) is proposed. The dynamic power consumption in CGSPFF is reduced by avoiding unnecessary input pulse transitions with clock gating. Two transistors in the main block of the flip-flop are eliminated to achieve low leakage power as well. Using the new clock pulse generator leads… (More)

This study concerns the existence of positive solutions to classes of boundary value problems of the form where ∆ denote the Laplacian operator, Ω is a smooth bounded domain in R N (N ≥ 2) with ∂Ω of class C 2 , and connected, and g(x, 0) < 0 for some x ∈ Ω (semipositone problems). By using the method of sub-super solutions we prove the existence of… (More)

- A. S. Seyedi, S. H. Rasouli, A. Amirabadi, Ali Afzali-Kusha
- ISCAS
- 2006

- Ali Abbasian, S. H. Rasouli, Ali Afzali-Kusha, Mehrdad Nourani
- ISCAS
- 2003

- A. Amirabadi, A. Chehelcheraghi, S. H. Rasouli, A. Seyedi, Ali Afzali-Kusha
- ISCAS
- 2006

- FLOP DMHLFF, S. H. Rasouli, Ali Afzali-Kusha, A. Khadem-zadeh, Maya Nourani
- 2004

In this paper a new low power flip-flop called Double-edge triggered Modified Hybrid Latch FlipFlop (DMHLFF) has been proposed and compared to previous flip-flops. DMHLFF is a low power, low area, and fast flip-flop. Power consumption is reduced by avoiding unnecessary internal node transition. Power consumption in clock tree is also reduced by decreasing… (More)

- G. Venkadeshkumar, K. Navanetha Pandiaraj, +14 authors T. Sullivan
- 2012

A low power pulse triggered ?ip?op (P-FF) design is done by the pulse generation control logic, an AND function, is removed from the critical path to facilitate a faster discharge operation. A simple two-transistor AND gate design is used to reduce the circuit complexity. A conditional pulse enhancement technique is devised to speed up the discharge along… (More)

- Mohammad Bagher Ghaemi, G. A. Afrouzi, S. H. Rasouli, M. Choubin
- Appl. Math. Lett.
- 2013

- S. H. Rasouli
- 2015

We study the existence of positive solution for the system −∆u = λa(x)[f(v)− 1 uα ], x ∈ Ω −∆v = λb(x)[g(v)− 1 vβ ], x ∈ Ω u = v = 0, x ∈ ∂Ω, where λ is a positive parameter, Ω is a bounded domain with smooth boundary, α, β ∈ (0, 1). Here a(x) and b(x) are C sing-changing functions that maybe negative near the boundary and f , g are C nondecreasing… (More)