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In this paper, a new flip-flop called Double-edge triggered Feedback Flip-Flop (DFFF) is proposed. The dynamic power consumption of DFFF is reduced by avoiding unnecessary internal node transition. The subthreshold current in the flip-flops is very low compared to other structures. Reducing the number of transistor in the stack and increasing the number of… (More)

This study concerns the existence of positive solutions to classes of boundary value problems of the form where ∆ denote the Laplacian operator, Ω is a smooth bounded domain in R N (N ≥ 2) with ∂Ω of class C 2 , and connected, and g(x, 0) < 0 for some x ∈ Ω (semipositone problems). By using the method of sub-super solutions we prove the existence of… (More)

In this paper, a new flip flop called clock gated static pulsed flip-flop (CGSPFF) is proposed. The dynamic power consumption in CGSPFF is reduced by avoiding unnecessary input pulse transitions with clock gating. Two transistors in the main block of the flip-flop are eliminated to achieve low leakage power as well. Using the new clock pulse generator leads… (More)

- Imran Ahmed Khan, Danish Shaikh, Mirza Tariq Beg, Xiaowen Wang, William H. Robinson, Peiyi Zhao +21 others
- 2013

This paper enumerates high speed design of RS & D-flip-flop using AlGaAs/GaAs MODFET. The proposed Flip Flop is having less number of transistors than existing designs. Simulation results show lowest average power and least delay than existing designs. This Flip-Flop having less number of transistors. It can be efficiently used in VLSI ICs. In the… (More)

In this note we are mainly concerned with existence result for semi-linear semipositone elliptic equation of the form ⎧ ⎨ ⎩ −Δu = λa(x)v α − c, x ∈ Ω, −Δv = λb(x)u β − c, x ∈ Ω, u = v = 0, x∈ ∂Ω, where Δ denote the Laplacian operator, Ω is a bounded domain in R N (N > 1) with ∂Ω of class C 2 , λ, c are positive parameters, α, β > 0 and the weight a(x), b(x)… (More)

An optimization approach for design of domino logic circuit using genetic algorithm is proposed in this paper. Simulation-based genetic algorithm is used to design of domino logic circuit to achieve a high accurate result. By the given noise margin, delay, leakage power and active power, the fitness function is defined and the genetic algorithm is used to… (More)