Learn More
We report Ge p-channel MOSFETs with a thin gate stack of Ge oxynitride and LTO on bulk Ge substrate without a Si cap layer. Excellent device characteristics (IV and CV) are achieved with subthreshold slope 82mV/dec. /spl sim/40% hole mobility enhancement is obtained over the Si control with a thermal SiO/sub 2/ gate dielectric. To our knowledge, this is the(More)
This paper presents spiral inductor structures optimized in a Cu-damascene VLSI interconnect technology with use of silicon, high-resistivity silicon (HRS), or sapphire substrates. Quality factors (Q) of 40 at 5.8 GHz for a 1.4 nH-inductor and 13 at 600 MHz for a 80 nH-inductor have been achieved.
N- and p-MOSFETs have been fabricated in strained Si on SiGe on insulator (SSOI) with high (15-25%) Ge content. Wafer bonding and H-induced layer transfer techniques enabled the fabrication of the high Ge content SiGe-on-insulator (SGOI) substrates. Mobility enhancement of 46% for electrons and 60-80% for holes (for 20%-25% Ge content) has been demonstrated(More)
  • 1