S . C . Rustagi

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In modern CMOS technologies, metal dummy fills are required to maintain metal density uniformity and to planarize the layers. As frequency increases, the effect of the metal dummy fills on the CMOS integrated circuits or components should be taken into account. This work presents experimental results of the effect of metal dummy fills on the microwave(More)
This work presents the fully lumped element model for wideband on-chip interconnects, with large scalability of line lengths up to 8000 mum, and widths down to 100 nm. Both the series and the shunt lumped elements of the model are determined based on the frequency asymptotic technique without any optimization. The equivalent lumped circuit is derived and(More)
A fully scalable and SPICE compatible wideband model of on-chip interconnects valid up to 110 GHz is presented in this paper. The series branches of the proposed multisegment model consist of an RL ladder network to capture the skin and proximity effects, as well as the substrate skin effect. Their values are obtained from a technique based on a modified(More)
An accurate and efficient method to extract an equivalent circuit model of a MOSFET is presented. Four-port measurements simplify the determination of important elements, such as the substrate networks. These measurements are also used to extract the MOSFET extrinsic parasitic elements. The accuracy of the model extraction is verified by simulation and(More)
In this work, we simulate silicon-on-insulator (SOI) multiple gate FinFET (MuGFET) with the design targeting for the ITRS 2004 specifications for NMOSFET. A detailed fully 3D simulation and analysis of the parasitic capacitances is performed for the first time to study the impact of scaling and pitch spacing. Unlike planar devices, FinFET scaling does not(More)
On-chip copper inductors, MIM capacitors and precision resistors in a novel, low-cost process are described. A CMOS transceiver for Bluetooth was realized with these new RF passive components and compared with the same IC realized in a commercial 0.35 /spl mu/m CMOS process with Al metalization. In a low-noise amplifier (LNA), a gain improvement of around 5(More)
In this paper, we present a vertical nanowire thin film transistor with gate-all-around architecture, fabricated using CMOS compatible processes. A novel method of fabricating polysilicon vertical nanowires of diameter as small as 30 nm using wet-etch is presented. Both n-type and p-type vertical poly-silicon nanowire transistors exhibit superior electrical(More)
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