Learn More
One of the biggest challenges for the VLSI circuits with 32-nm-technology nodes and beyond is to overcome the issue of catastrophic increases in power consumption due to short-channel effects (SCEs). Fortunately, "independent" double-gate (DG) FinFETs (named "4-terminal-FinFET" because of its four terminals; source, drain, gate 1 and gate 2) have a(More)
Ultra-scaled FinFET transistors bear unique fingerprint-like device-to-device differences attributed to random single impurities. Through correlation of experimental data with multimillion atom simulations in NEMO 3-D, we can identify the impurity's chemical species and determine their concentration, local electric field and depth below the Si/SiO 2(More)
The mechanism responsible for the short-channel electron mobility (e<sup>$</sup>mobility) abnormal degradation in n-type tall fins multiple-gate field-effect transistors (MuGFETs) has been identified. RF-CV measurement, mobility extraction, and 1/f noise measurements have been performed and point to a larger process related density of traps (N <sub>t</sub>)(More)
We present atomistic simulations of the D 0 to D − charging energies of a gated donor in silicon as a function of applied fields and donor depths and find good agreement with experimental measurements. A self-consistent field large-scale tight-binding method is used to compute the D − binding energies with a domain of over 1.4 million atoms, taking into(More)
We report the observation of lifetime-enhanced transport (LET) based on perpendicular valleys in silicon by transport spectroscopy measurements of a two-electron system in a silicon transistor. The LET is manifested as a peculiar current step in the stability diagram due to a forbidden transition between an excited state and any of the lower energy states(More)
Channel conductance measurements can be used as a tool to study thermally activated electron transport in the sub-threshold region of state-of-art FinFETs. Together with theoretical Tight-Binding (TB) calculations, this technique can be used to understand the evolution of source-to-channel barrier height (E b) and of active channel area (S) with gate bias(More)
In this paper, we investigate for the first time the impact of raised source/drain on the short channel current enhancement of MuGFET devices on super critical strained SSOI (SC-SSOI). Short channel nMOS drive current can be improved up to 15% and even 50% in the case of high tensile 30 nm SSOI substrates. We also show that SC-SSOI has a higher sensitivity(More)
Despite their excellent control of short channel effects, FinFETs suffer from different trade-offs in the mixed-signal domain, with respect to planar devices. For the first time, we report a complete and comprehensive comparative analysis showing that these trade-offs can be alleviated in advanced FinFET technology. As such, higher voltage gain and(More)
The presence of interface states at the MOS interface is a well-known cause of device degradation. This is particularly true for ultra-scaled FinFET geometries where the presence of a few traps can strongly influence device behavior. Typical methods for interface trap density (Dit) measurements are not performed on ultimate devices, but on custom designed(More)
—Thermally activated subthreshold transport has been investigated in undoped triple-gate MOSFETs. The evolution of the barrier height and of the active cross-sectional area of the channel as a function of gate voltage has been determined. The results of our experiments and of the tight-binding simulations we have developed are both in good agreement with(More)