S. Biesemans

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We report on spectroscopy of a single dopant atom in silicon by resonant tunneling between source and drain of a gated nanowire etched from silicon on insulator. The electronic states of this dopant isolated in the channel appear as resonances in the low temperature conductance at energies below the conduction band edge. We observe the two possible charge(More)
The presence of interface states at the MOS interface is a well-known cause of device degradation. This is particularly true for ultra-scaled FinFET geometries where the presence of a few traps can strongly influence device behavior. Typical methods for interface trap density (Dit) measurements are not performed on ultimate devices, but on custom designed(More)
We report the observation of lifetime-enhanced transport (LET) based on perpendicular valleys in silicon by transport spectroscopy measurements of a two-electron system in a silicon transistor. The LET is manifested as a peculiar current step in the stability diagram due to a forbidden transition between an excited state and any of the lower energy states(More)
R. Rahman*, G. P. Lansbergen, J. Verduijn, 3 G. C. Tettamanzi, 3 S. H. Park, N. Collaert, S. Biesemans, G. Klimeck, L. C. L. Hollenberg, and S. Rogge 3 Advanced Device Technologies, Sandia National Laboratories, Albuquerque, NM 87185, USA Kavli Institute of Nanoscience, Delft University of Technology, Lorentzweg 1, 2628 CJ Delft, The Netherlands Centre for(More)
The mechanism responsible for the short-channel electron mobility (e<sup>$</sup>mobility) abnormal degradation in n-type tall fins multiple-gate field-effect transistors (MuGFETs) has been identified. RF-CV measurement, mobility extraction, and 1/f noise measurements have been performed and point to a larger process related density of traps (N <sub>t</sub>)(More)
Ultra-scaled FinFET transistors bear unique fingerprint-like device-to-device differences attributed to random single impurities. Through correlation of experimental data with multimillion atom simulations in NEMO 3-D, we can identify the impurity’s chemical species and determine their concentration, local electric field and depth below the Si/SiO2(More)
One of the biggest challenges for the VLSI circuits with 32-nm-technology nodes and beyond is to overcome the issue of catastrophic increases in power consumption due to short-channel effects (SCEs). Fortunately, "independent" double-gate (DG) FinFETs (named "4-terminal-FinFET" because of its four terminals; source, drain, gate 1 and gate 2) have a(More)
Channel conductance measurements can be used as a tool to study thermally activated electron transport in the sub-threshold region of state-of-art FinFETs. Together with theoretical Tight-Binding (TB) calculations, this technique can be used to understand the evolution of source-to-channel barrier height (E b) and of active channel area (S) with gate bias(More)
Despite their excellent control of short channel effects, FinFETs suffer from different trade-offs in the mixed-signal domain, with respect to planar devices. For the first time, we report a complete and comprehensive comparative analysis showing that these trade-offs can be alleviated in advanced FinFET technology. As such, higher voltage gain and(More)
The Kondo effect has been observed in a single gate-tunable atom. The measurement device consists of a single As dopant incorporated in a silicon nanostructure. The atomic orbitals of the dopant are tunable by the gate electric field. When they are tuned such that the ground state of the atomic system becomes a (nearly) degenerate superposition of two of(More)