S.A. Campbell

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Using a new technique in forming the cubic single-crystal silicon nanoparticles that are about 40 nm on a side, the authors have demonstrated a vertical-flow surround-gate Schottky-barrier transistor. This approach allows the use of well-known approaches to surface passivation and contact formation within the context of deposited single-crystal materials(More)
Suitable replacement materials for ultrathin SiO/sub 2/ in deeply scaled MOSFETs such as lattice polarizable films, which have much higher permittivities than SiO/sub 2/, have bandgaps of only 3.0 to 4.0 eV. Due to these small bandgaps, the reliability of these films as a gate insulator is a serious concern. Ramped voltage, time dependent dielectric(More)
Charge in HfO/sub 2/ gate stacks grown from various metal-organic chemical vapor deposition sources has been studied using nMOS capacitors with a damage-free Cr gate process. It is found that the charge in the stack is mainly concentrated at the interfaces between materials. The effect of postdeposition anneal depends on the high-/spl kappa/ film-deposition(More)
This paper demonstrates that an in-line SF<sub>6</sub> etching process, which is known to produce high concentrations of free fluorine radicals, can be used to size the nanocrystals without creating a polymeric surface layer. As with the CF<sub>4</sub> process, Si-NCs fabricated by this process luminesce well, with the luminescent peak wavelength determined(More)
Junction field effect light emitting transistors (JFELET) were fabricated using silicon quantum dots in a conducting polymer matrix. The quantum dots with photoluminescence emission centered at 650 nm were used. I-V and light emission characteristics for typical light emitting transistors are presented.
Single crystal semiconductor nanoparticles provide a novel path to monolithic integration of lattice mismatched and even chemically incompatible materials. This in turn provides an avenue to reliable, high performance, integrated information systems that go well beyond today's integrated circuits. This paper reviews aspects of this work including single(More)
  • Zhihong Zhang, Min Li, S.A. Campbell
  • IEEE Transactions on Electron Devices
  • 2005
Charge in metal-organic chemical vapor deposition-grown HfO/sub 2/ gate stacks has been systematically studied using nMOS capacitors. It is found that, for these films, the charge in the stack is mainly concentrated at the interfaces between the layers and is negative at the HfO/sub 2//interfacial layer (IL) interface and positive at the Si/IL interface. In(More)
Tunneling leakage limits the scaling of SiO/sub 2/ to about 1.5 nm. Well behaved transistors have previously been made with MOCVD-deposited TiO/sub 2/ using the thermal decomposition of titanium tetrakis isopropoxide. However, after the required O/sub 2/ anneal, these devices have a 2.5 nm amorphous interfacial layer which severely limits the capacitance.(More)
This study demonstrates that in-line etching processes can be created to size the nanoparticles and produce a surface passivation layer. Photoluminescence measurements have been carried out to examine the dry etching process. It is found that the PL of Si nanocrystals (Si-NCs) blueshifts when the dry etching reduces the size of Si-NCs, consistent with the(More)
This letter presents a systematic investigation of charge in HfO/sub 2/ gate stacks. Assuming that the majority of charge is associated with the stack interfaces, it is found that the charge at the HfO/sub 2//interfacial layer (IL) interface is negative while the charge at the Si/IL interface is positive. In general, the calculated charge densities at both(More)