Sébastien Bilavarn

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Early performance feedback and design space exploration of complete field-programmable gate array (FPGA) designs are still time consuming tasks. This paper proposes an original methodology based on estimations to reduce the impact on design time. It promotes a hierarchical exploration to mitigate the complexity of the exploration process. Therefore, this(More)
Recent embedded systems and SOCs design is confronted with the problem of the so-called productivity gap. In order to cope with this problem, authors emphasize on using UML as a system level language, so higher level of abstraction is achieved. However UML in its current form has not yet achieved the maturity necessary to enable its efficient use within(More)
Rapid evaluation and design space exploration at the algo-rithmic level are important issues in the design cycle. In this paper we propose an original area vs delay estimation methodology that targets reconfigurable architectures. Two main steps compose the estimation flow: i) the structural estimation which is technological independent and performs an(More)
In the context of embedded systems development, two important challenges are the efficient use of silicon area and the energy consumption minimization. Hardware accelerated tasks allow to reduce energy consumption of several orders of magnitude, compared to software execution, but these tasks require silicon area and consume power even when they are unused(More)
A new performance estimation technique for FPGA implementation based designs is presented. The interest and originality of the method is to rapidly test a great number of implementation solutions while staying independent as far as possible of the technology used, and to include power consumption estimation. Thanks to this method, the designer can quickly(More)
A lot of task scheduling algorithms and power management policies have been developed based on simplistic power models, which rarely take into account the effects of the power consumptions of the different components of a real system. Most of the models on which the study of the DVFS scheduling is based, make the assumption that the power consumption of a(More)
This paper presents a new design methodology able to bridge the gap between an abstract specification and a heterogeneous recon-figurable architecture. The EPICURE contribution is the result of a joint study on abstraction/refinement methods and a smart reconfigurable architecture within the formal Esterel design tools suite. The original points of this(More)
—Nowadays, System-on-Chip architectures are composed of several execution resources which support complex applications. These applications increasingly need flexibility to adapt to their environment. Embed a reconfigurable resource in these SoC enables to flexibilize the hardware by sharing silicon area and limiting the cost of the global circuit. Partial(More)