Ryuta Kawano

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This paper explores the grain of domain size of an energy efficient coarse grained reconfigurable array called CMA (Cool Mega Array). By using Genetic Algorithm based body bias assignment method, the leakage reduction of various grain size was evaluated. As a result, a domain with 2×1 PEs achieved about 40% power reduction with a 6% area overhead.
Distributed routing methods with small routing tables are scalable design on irregular networks for large-scale High Performance Computing (HPC) systems. Recently proposed compact routing methods, however, do not guarantee deadlock-freedom. Cyclic channel dependencies on arbitrary routing are typically removed with multiple Virtual Channels (VCs). However,(More)
In recent many-core architectures, the number of cores has been steadily increasing and thus the network latency between cores becomes an important issue for parallel application programs. Because packet-switched network structures are widely used for core-to-core communications, a topology among cores has a major impact on the network latency. It has been(More)
A T-bit/s ATM switching system architecture, called the OPTlMA switch, is proposed. This system is scalable and quasi-non-blocking by virtue of its self-load-balancing mechanism and high-speed interconnection effect. The selfload-balancing mechanism prevents overloading in the switch by automatically checking and balancing the internal load. An experimental(More)
End-to-end network latency has become an important issue for parallel application on large-scale high performance computing (HPC) systems. It has been reported that randomly-connected inter-switch networks can lower the end-to-end network latency. The trade-off is a large amount of routing information. For irregular networks, minimal routing is achieved by(More)
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