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—This paper presents a 60-GHz direct-conversion RF front-end and baseband transceiver including analog and digital circuitry for PHY functions. The 65-nm CMOS front-end consumes 319 and 223 mW in transmitting and receiving mode, respectively. It is capable of more than 7-Gb/s 16QAM wireless communication for every channel of the 60-GHz standards, which can(More)
SUMMARY This paper presents measurement of on-chip coupling between PA and LNA integrated on Si CMOS substrate, which is caused by substrate coupling, magnetic coupling, power-line coupling, etc. These components are decomposed by measurements using diced chips. The result reveals that the substrate coupling is the most dominant in CMOS chips and the total(More)
This paper presents a 60-GHz direct-conversion transceiver in 65 nm CMOS technology. By the proposed gain peaking technique, this transceiver realizes good gain flatness and is capable of more than 7 Gbps in 16QAM wireless communication for all channels of IEEE802.11ad standard within EVM of around -23 dB. The transceiver consumes 319mWin transmitting and(More)
— This paper presents a 16QAM direct-conversion transceiver in 65 nm CMOS, which is capable of 60-GHz wireless standards. The capacitive cross-coupling neutralization contributes a high common-mode rejection and a high reverse isolation, and a fully-balanced mixer can improve the error vector magnitude due to the reduced local leakage. The maximum data(More)
—This paper proposes the method of varactor cross-couplng with adaptive bias. The capacitive cross-coupling neu-tralization contributes to improve power gain and reverse isolation. The optimized capacitance of cross-coupled PA depends heavily on the input power. Thus, the varacter is used and adaptive bias is obtained by the feedback of the input power. The(More)
This paper presents a digitally-calibrated 60-GHz direct-conversion transceiver. To improve the error vector magnitude (EVM) performance over the wide bandwidth, a digital calibration technique is applied. The 60-GHz transceiver implemented by 65 nm CMOS achieves the maximum data rates of 20 Gb/s in 16QAM mode. The transmitter and receiver consume 351 mW(More)
A pure CMOS threshold voltage reference (V<inf>TR</inf>) circuit achieves temperature(T) coefficient of 5 &mu;V/&#176;C (T=-60~+100&#176;C) and supply voltage (V<inf>DD</inf>) sensitivity of 0.1 mV/V (V<inf>DD</inf>=3~5 V). The combination of subthreshold current characteristics and different operating modes in n-MOSFETs provides a small voltage and(More)