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In this paper we propose a new methodology, called parametric on chip variation (POCV) analysis, to determine local process variation effects on the timing of designs. The proposed methodology requires relative delay and parasitic variations of cells and interconnects, respectively. Once this information is provided, delays and arrival times are propagated(More)
Complex design rules, low-power circuitry design techniques, and signal integrity issues are just a few of the advanced-node challenges impacting design closure. While timing analysis and signoff and power integrity analysis and signoff are critical to successful design closure, both of these steps can also be quite time-consuming and resource-intensive. On(More)
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