Ru-Hua Chang

Learn More
Integrating Multi-Processor System-on-Chips (MP-SoCs) with 3D-stacked reconfigurable SRAM tiles has been proposed for embedded systems with high memory demands. At runtime, the SRAM tiles are configured into several memory areas, which can be reconfigured according to the dynamic behavior of the system. Targeting this architecture, in this paper, we propose(More)
  • 1