Roy P. Paily

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In this paper, we present a simulation study of analog circuit performance parameters for a symmetric double-gate junctionless transistor (DGJLT) using dual-material gate along with high- k spacer dielectric (DMG-SP) on both sides of the gate oxides of the device. The characteristics are demonstrated and compared with DMG DGJLT and single-material(More)
This work focuses on the VLSI design aspect of high- speed maximum a posteriori (MAP) probability decoders which are intrinsic building-blocks of parallel turbo decoders. For the logarithmic-Bahl-Cocke-Jelinek-Raviv (LBCJR) algorithm used in MAP decoders, we have presented an ungrouped backward recursion technique for the computation of backward state(More)
This paper addresses design, hardware implementation and performance testing of AES algorithm. An optimized code for the Rijndael algorithm with 128-bit keys has been developed. The area and throughput are carefully trading off to make it suitable for wireless military communication and mobile telephony where emphasis is on the speed as well as on area of(More)
In high speed flash ADCs, the thermometer coded output of the comparators is converted to binary code by a thermometer-to-binary decoder using a ROM. The ROM is simple and straightforward to design but it requires bubble error correction/suppression circuitry. A novel ROM architecture suitable for high speed operation with bubble error suppression is(More)
Maximum a posteriori probability (MAP) decoder is an integral part of the most exciting error correcting turbo decoders. A high speed architecture for MAP decoder is an essential entity for the design of high throughput turbo decoder which is widely used in the recent wireless communication standards. In this paper, a new sliding window approach for the(More)
This paper presents architecture of block-level-parallel layered decoder for irregular LDPC code. It can be reconfigured to support various block lengths and code rates of IEEE 802.11n (WiFi) wireless-communication standard. We have proposed efficient comparison techniques for both column and row layered schedule and rejection-based high-speed circuits to(More)
This paper presents the effects of high-temperature on the major digital and analog performance parameters of a 20-nm channel length n-type symmetric double-gate junctionless transistor (DGJLT) with the help of extensive device simulations. The characteristics are compared with conventional inversion mode counterpart i.e., double-gate transistor (DGMOS) of(More)
In this paper, the performance of a short channel symmetric double-gate junctionless transistor (DGJLT) is reported at lower drain voltage aiming low power digital applications. The performance parameters namely drain current (I<sub>D</sub>), threshold voltage (V<sub>T</sub>), subthreshold slope (SS), drain induced barrier lowering (DIBL), and ON-state to(More)