Learn More
This paper introduces the architecture of an AVS (audio video coding standard working group of China) hardware decoding system. The system includes system layer decoding, video decoding and audio decoding. It supports 720p/1080i HD (high-definition) format real-time decoding. A VLSI chip is designed by using this architecture.
HEVC (High Efficiency Video Coding) has recently been published as the next generation video coding standard. Compared with previous standards, the coding efficiency is greatly improved at the cost of much higher codec complexity. On the other hand, ARM with SIMD (Single Instruction Multiple Data) instructions is widely deployed on mobile platform, which(More)
H.264/AVC is the latest standard for video coding drafted jointly by the ISO/IEC Moving Picture Experts Group and the ITU-T Video Coding Experts Group. H.264/AVC provides up to 50% gains in compression efficiency over a wide range of bit rates and video resolutions compared to previous standards. On the other hand, the decoder complexity is about four times(More)
This paper presents a novel no-reference blocking artifacts metric using selective gradient and plainness (BAM_SGP) measures for DCT-coded images. A boundary selection criterion is introduced to distinguish the blocking artifacts boundaries from the true-edge boundaries, which ensures that the most potential artifacts boundaries are involved in the(More)
In order to reduce the bit rate of video signals, motion compensation prediction is applied in modern video coding technology. This is a form of temporal redundancy reduction in which the current coding frame is predicted by a motion compensated prediction from some other already decoded frames according to motion vector. As real motion has arbitrary(More)
This paper proposes a high efficiency memory controller for an H.264 HDTV decoder with synchronous DRAMs. As H.264 adopts tree structured (supports small block size) motion compensation, the bandwidth requirement of an H.264 HDTV decoder is higher than previous video processing algorithms. This requires to be optimized. Based on H.264 decoding data access(More)
A spatio-temporal autoregressive model is proposed in this paper to address the problem of frame rate up conversion. Every pixel in a skipped frame is generated as a linear combination of pixel values from forward and backward reference frames. At the beginning of the presented scheme, the coarse model parameters are computed according to the given initial(More)
We propose a novel compact representation for stereoscopic videos - a 2D video and its depth cues. Depth cues are derived from an interactive labeling process during 2D-to-3D video conversion, they are contour points of foreground objects and a background geometric model. By using such cues and image features of 2D video frames, depth maps of the frames can(More)
In this paper, an auto-regressive (AR) model is proposed to generate the side information for low-delay distributed video coding (DVC). The side information generation of current Wyner-Ziv (WZ) frame t consists of two forward AR interpolations. First, each pixel within the rebuilt frame 1 t − is approximated as a linear combination of pixels within a(More)