Ronald Spilka

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To enhance the performance of a switched-capacitor sigma-delta ADC we present a digitally trimmable on-chip voltage reference with a minimum step size in the range of 1-2mV@1.S-2.SV. Due to a multi-stage calibration scheme the output voltage of the reference could be additionally adjusted over a wide range of SOO-700mV@1.7-2.1V. This can be useful to later(More)
In this paper an automatically generated VHDL-Code of a Delta-Sigma-Modulator for a digital design-flow is presented. For the verification of the design-flow, an example system - a digital 4<sup>th</sup>-order Delta-Sigma-Modulator - in a standard 0.35&#x00B5;m technology is manufactured. As a proof of concept the simulation is compared to the measurement(More)
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