Ronald Hecht

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Due to their layered approach, Networks-on-Chip (NoC) are a promising communication backbone in the field of heterogeneous dynamically reconfigurable systems. In this paper a future FPGA architecture is discussed having a hardwired NoC as an additional high-level routing resource. Instead of implementing on-chip interconnection with valuable recon-figurable(More)
Managing reconfigurable hardware resources at runtime is expected to be a new task for future operating systems. But due to the mixture of parallel and sequential parts of dynamically reconfigurable applications, it is not entirely clear so far, how to use and to program such systems. In this paper, a new interpretation of dynamically reconfigurable(More)
—During the last years, Networks-on-Chip (NoCs) have become a true alternative for the design of complex integrated Systems-on-Chip (SoC). Much effort has been spent for research on functionalities, mechanisms, and Quality-of-Service (QoS) features in NoCs. Hence, a broad and multi-faceted design space exists but leaves open, which mechanisms and design(More)
Selbst mit den neuesten Modellierungswerkzeugen und dem Einzug von Ob-jektorientierung und Abstraktion in die Hardware-Entwicklung ist der Aufwand für die Verifikation immer noch bestimmend für den gesamten Entwurfsprozess. Wiederverwendbarkeit und Flexibilität sind deshalb aus ökonomischer Sicht unabdingbar. Es wird eine SystemC-Verifikationsumgebung(More)
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