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Due to their layered approach, Networks-on-Chip (NoC) are a promising communication backbone in the field of heterogeneous dynamically reconfigurable systems. In this paper a future FPGA architecture is discussed having a hardwired NoC as an additional high-level routing resource. Instead of implementing on-chip interconnection with valuable recon-figurable(More)
During the last years, networks-on-chip (NoCs) have become a true alternative for the design of complex integrated systems-on-chip (SoC). Much effort has been spent for research on functionalities, mechanisms, and quality-of-service (QoS) features in NoCs. Hence, a broad and multi-faceted design space exists but leaves open, which mechanisms and design(More)
Managing reconfigurable hardware resources at runtime is expected to be a new task for future operating systems. But due to the mixture of parallel and sequential parts of dynamically reconfigurable applications, it is not entirely clear so far, how to use and to program such systems. A new interpretation of dynamically reconfigurable applications is(More)
Partial dynamic reconfigurability of modern FPGAs holds the potential of realizing autonomous and highly flexible systems-on-chip (SoC). Current devices can be configured with several partial bitfiles and replace particular ones on demand. But these precompiled bitfiles seriously lack flexibility: they are hardly relocatable and not adjustable. In other(More)
Since the demands on performance and flexibility for packet processing are rising permanently, FPGAs and ASICs are the preferred hardware platform due to their high computation power. But existing solutions for packet processing in FPGAs and ASICs base on conventional, synchronous bus systems or pipelined data path architectures, which are only little(More)
Meeting the high demands of outer space missions requires immense efforts and is exceedingly time consuming. For the latest accomplished missions, the engineering of the hardware and computing systems took years and must be completed before launch. The architecture of a Network on Chip (NoC) based System on Chip (SoCs) is presented in this paper. These SoCs(More)
Non-uniform sampling promises increased equivalent sampling rates with reduced overall hardware costs. Each device applying non-uniform sampling must use special circuits and architectures to achieve a correct and predictable sampling scheme with respect to time instant placement. The architecture of an ASIC implementation for non-uniform sampling varies(More)
Selbst mit den neuesten Modellierungswerkzeugen und dem Einzug von Ob-jektorientierung und Abstraktion in die Hardware-Entwicklung ist der Aufwand für die Verifikation immer noch bestimmend für den gesamten Entwurfsprozess. Wiederverwendbarkeit und Flexibilität sind deshalb aus ökonomischer Sicht unabdingbar. Es wird eine SystemC-Verifikationsumgebung(More)