Ronald F. DeMara

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NULL Convention Logic (NCL) provides an asynchronous design methodology employing dual-rail signals, quad-rail signals, or other Mutually Exclusive Assertion Groups (MEAGs) to incorporate data and control information into one mixed path. In NCL, the control is inherently present with each datum, so there is no need for worsecase delay analysis and control(More)
An autonomous self-repair approach for SRAM-based FPGAs is developed based on Competitive Runtime Reconfiguration (CRR). Under the CRR technique, an initial population of functionally identical (same inputoutput behavior), yet physically distinct (alternative design or place-and-route realization) FPGA configurations is produced at design time. At run-time,(More)
Most evolutionary approaches to fault recovery in FPGAs focus on evolving alternative logic configurations as opposed to evolving the intra-cell routing. Since the majority of transistors in a typical FPGA are dedicated to interconnect, nearly 80% according to one estimate, evolutionary fault-recovery systems should benefit by accommodating routing. In this(More)
A fault tolerance model called Triple Modular Redundancy with Standby (TMRSB) is developed which combines the two popular fault tolerance techniques of Triple Modular Redundancy (TMR) and Standby (SB) fault tolerance. In TMRSB systems, each module of a TMR arrangement has access to several independent standby configurations. When a fault is detected in a(More)
Most evolutionary approaches to fault recovery in FPGAs focus on evolving alternative logic configurations as opposed to evolving the intra-cell routing. Since the majority of transistors in a typical FPGA are dedicated to interconnect, nearly 80% according to one estimate, evolutionary faultrecovery systems should benefit by accommodating routing. In this(More)
Spin-Transfer Torque Random Access Memory (STT-RAM) has been identified as an advantageous candidate for on-chip memory technology due to its high density and ultra low leakage power. Recent research progress in Magnetic Tunneling Junction (MTJ) devices has developed Multi-Level Cell (MLC) STT-RAM to further enhance cell density. To avoid the write(More)
As the devices are scaling down, the combinational logic will become susceptible to soft errors. The conventional soft error tolerant methods for soft errors on combinational logic do not provide enough high soft error tolerant capability with reasonably small performance penalty. This paper investigates the feasibility of designing quasi-delay insensitive(More)
Self-timed logic design methods are developed using Threshold Combinational Reduction (TCR) within the NULL Convention Logic (NCL) paradigm. NCL logic functions are realized using 27 distinct transistor networks implementing the set of all functions of four or fewer variables, thus facilitating a variety of gatelevel optimizations. TCR optimizations are(More)
The capabilities of current fault-handling techniques for Field Programmable Gate Arrays (FPGAs) develop a descriptive classification ranging from simple passive techniques to robust dynamic methods. Fault-handling methods not requiring modification of the FPGA device architecture or user intervention to recover from faults are examined and evaluated(More)