TATOO is an industrial interactive timing analysis system evolved from recently developed false path elimination algorithms. These have been extended to perform more complex searches that facilitate the rapid survey of a network. An automatic test pattern generation mechanism which exercises the statically sensitizable paths has been developed. This forms a… (More)
Digital MOS transistor designs are imported into an environment of cell-based tools by division of the design into gate-level components followed by the automatic generation of their logical and timing views. Symbolic switch-level analysis divides the design into channel-connected components and provides estimates of their logical behavior. Then, electrical… (More)
LibQA is a quality assurance tool for VHDL synthesis and simulation models which also performs timing characterization. The synthesis model is translated into an FSM, then graph exploration generates stimuli for VHDL and electrical simulation. Function, propagation delay, timing constraint violation, and hazard response are all tested.