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Trends in VLSI technology scaling demand that future computing devices be narrowly focused to achieve high performance and high efficiency, yet also target the high volumes and low costs of widely applicable general purpose designs. To address these conflicting requirements, we propose a modular reconfigurable architecture called Smart Memories, targeted at(More)
Scaling trends of logic, memories, and interconnect networks lead towards dense many-core chips. Unfortunately, process yields and reticle sizes limit the scalability of large single-chip systems. Multi-chip systems break free of these areal limits, but in turn require enormous chip-to-chip bandwidth. The "macrochip" concept presented here integrates(More)
A proposed supercomputer-on-a-chip with optical interconnections between processing elements will require development of new lower-energy optical components and new circuit architectures that match electrical datapaths to complementary optical interfaces. ABSTRACT | We present a computing microsystem that uniquely leverages the bandwidth, density, and(More)
Using low parasitic microsolder bumping, we hybrid integrated efficient photonic devices from different platforms with advanced 40 nm CMOS VLSI circuits to build ultra-low power silicon photonic transmitters and receivers for potential applications in high performance inter/intra-chip interconnects. We used a depletion racetrack ring modulator with improved(More)
Displaying the real-time behavior of critical signals on VLSI chips is difficult and can require expensive test equipment. We present a simple sampling technique to display the analog waveforms of high bandwidth on-chip signals on a laboratory oscilloscope. It is based on the subsampling of periodic signals as proposed in [1]. This circuit was used to(More)
Optical interconnects are useful for high-performance electronic computing systems when the number-of-channels, the bit-rate per channel, the channel density, and the communication distance of electrical links are simultaneously stressed. We review the near-term and longer term opportunities for optical communication at the chassis, chip-package and silicon(More)
We report the first sub-picojoule per bit (400fJ/bit) operation of a silicon modulator intimately integrated with a driver circuit and embedded in a clocked digital transmitter. We show a wall-plug power efficiency below 400microW/Gbps for a 130nm SOI CMOS carrier-depletion ring modulator flip-chip integrated to a 90nm bulk Si CMOS driver circuit. We also(More)