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A proposed high speed generic floating point algorithm for 12-Bit Architecture is consist of adder, subtractor, multiplier, divisor, square root, and cube root modules. A novel algorithm was proposed for each modules using VHDL to optimize the speed and area as well as to attain the highest maximum operating frequency. A top down approach was applied for… (More)
Delay estimation is considered as one of the critical issues in the development of any Very Large Scale Integration (VLSI) design algorithms. It is also known as one of the factors to analyze in the design of high performance integrated circuit. Neither of these is usually applied to observe the performance of various VLSI topologies. High performance… (More)