Learn More
  • Junheng Zhu, Makrand Mahalley, +5 authors Pavan Kumar Hanumolu
  • 2017
This paper presents a novel oscillator architecture that uses a low frequency temperature stable clock generated by a low power RC relaxation oscillator to improve the temperature stability of a low noise ring oscillator. Fabricated in 65nm CMOS process, the prototype oscillator consumes 197 to 452µW across an output frequency range of 45-to-75MHz.(More)
A voltage mode transmitter employs pulse width modulation (PWM) based equalization of NRZ input data at 5 Gb/s and compensates 28 dB channel loss at 2.5 GHz. Fabricated in a 90 nm CMOS process, the proposed transmitter achieves a horizontal eye opening of 0.3UI with BER&lt;; 10<sup>-12</sup> and consumes only 16 mW power of which 2.5 mW is consumed by the(More)
—In this project variable time step integration method has been successfully implemented using Gear's method and interfaced with an basic SPICE-like simulator myspice. The order of integration is user defined and can be set between 1 to 6.the integration method been tested with stiff circuits and relative performance comparison has been done between fixed(More)