Roman Staszewski

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We present a single-chip fully compliant Bluetooth radio fabricated in a digital 130-nm CMOS process. The transceiver is architectured from the ground up to be compatible with digital deep-submicron CMOS processes and be readily integrated with a digital baseband and application processor. The conventional RF frequency synthesizer architecture, based on the(More)
We present the receiver in the first single-chip GSM transceiver that incorporates full integration of quad-band receiver, transmitter, memory, power management, dedicated ARM processor and RF built-in self test in a 90 nm digital CMOS process. The architecture uses direct RF sampling in the receiver and an all-digital PLL in the transmitter. The receive(More)
This paper proposes and describes a new software and application programming interface view of an RF transceiver. It demonstrates benefits of using highly programmable digital control logic in an RF wireless system realized in a digital nanoscale CMOS process technology. It also describes a microprocessor architecture design in Digital RF Processor (DRPTM)(More)
This paper proposes and describes a new software and application programming interface view of an RF transceiver as implemented in the first single-chip GSM radio in 90 nm CMOS. It demonstrates benefits of using programmable digital control logic in deep-submicron CMOS RF system. It also describes a micro-processor architecture design in digital RF(More)
We describe a simulation technique that uses an event-driven VHDL simulator to model an RF wireless transmitter. The technique is well suited to investigate complex interactions in large SoC systems, where traditional RF and analog simulation tools do not work effectively. The oscillator phase noise characteristics are described using time-domain equations.(More)
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