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Reversible logic is the basis for several emerging technologies such as quantum computing, optical computing, or DNA computing and has further applications in domains like low-power design and nanotechnologies. However, current methods for the synthesis of reversible logic are limited, i.e. they are applicable to relatively small functions only. In this(More)
Due to the rapidly growing size of integrated circuits, there is a need for new algorithms for automatic test pattern generation (ATPG). While classical algorithms reach their limit, there have been recent advances in algorithms to solve Boolean Satisfiability (SAT). Because Boolean SAT solvers are working on conjunctive normal forms (CNFs), the problem has(More)
Many optimisation problems in circuit design, in the following also refereed to as VLSI CAD, consist of mutually dependent sub-problems, where the resulting solutions must satisfy several requirements. Recently, a new model for Multi-Objective Optimisation (MOO) for applications in Evolutionary Algorithms (EAs) has been proposed. The search space is(More)
It is a widely supported prediction that conventional computer hardware technologies are going to reach their limits in the near future. Thus, to further satisfy the needs for more computational power, alternatives are required that go beyond the scope of conventional technologies. Reversible logic marks a promising new direction where all operations are(More)
In many verification techniques fast functional evaluation of a Boolean network is needed. We investigate the idea of using Binary Decision Diagrams (BDDs) for functional simulation. The area-time trade-off that results from different minimization techniques of the BDD is discussed. We propose new minimization methods based on dynamic reordering that allow(More)
1 In most real world optimization problems several optimization goals have to be considered in parallel. For this reason, there has been a growing interest in Multi-Objective Optimization (MOO) in the past years. Several alternative approaches have been proposed to cope with the occurring problems, e.g. how to compare and rank the different elements. The(More)
Automatic test pattern generation (ATPG) based on Boolean satisfiability (SAT) has been proposed as an alternative to classical search algorithms. SAT-based ATPG turned out to be more robust and more effective by formulating the problem as a set of equations. In this paper, we present an efficient ATPG algorithm that makes use of powerful SAT-solving(More)
We present a technique to derive fully testable circuits under the stuck-at fault model (SAFM) and the path-delay fault model (PDFM). Starting from a function description as a binary decision diagram, the netlist is generated by a linear time mapping algorithm. Only one additional input and one inverter are needed to achieve 100% testable circuits under(More)