#### Filter Results:

- Full text PDF available (478)

#### Publication Year

1992

2017

- This year (26)
- Last 5 years (224)
- Last 10 years (394)

#### Publication Type

#### Co-author

#### Journals and Conferences

#### Data Set Used

#### Key Phrases

Learn More

- Robert Wille, Daniel Große, Lisa Teuber, Gerhard W. Dueck, Rolf Drechsler
- ISMVL
- 2008

Synthesis of reversible logic has become an active research area in the last years. But many proposed algorithms are evaluated with a small set of benchmarks only. Furthermore, results are often documented only in terms of gate counts or quantum costs, rather than presenting the specific circuit. In this paper RevLib (www.revlib.org) is introduced, an… (More)

- Robert Wille, Rolf Drechsler
- 2009 46th ACM/IEEE Design Automation Conference
- 2009

Reversible logic is the basis for several emerging technologies such as quantum computing, optical computing, or DNA computing and has further applications in domains like low-power design and nanotechnologies. However, current methods for the synthesis of reversible logic are limited, i.e. they are applicable to relatively small functions only. In this… (More)

- Rolf Drechsler, Andisheh Sarabi, Michael Theobald, Bernd Becker, Marek A. Perkowski
- 31st Design Automation Conference
- 1994

An efficient package for construction of and operation on ordered Kronecker Functional Decision Diagrams (OKFDD) is presented. OKFDDs are a generalization of OBDDs and OFDDs and as such provide a more compact representation of the functions than either of the two decision diagrams. In this paper basic properties of OKFDDs and their efficient representation… (More)

- Raik Brinkmann, Rolf Drechsler
- VLSI Design
- 2002

Satisfiability of complex word-level formulas often arises as a problem in formal verification of hardware designs described at the register transfer level (RTL). Even though most designs are described in a hardware description language (HDL), like Verilog or VHDL, usually this problem is solved in the Boolean domain, using Boolean solvers. These engines… (More)

- Daniel Große, Robert Wille, Gerhard W. Dueck, Rolf Drechsler
- IEEE Transactions on Computer-Aided Design of…
- 2009

Synthesis of reversible logic has become a very important research area in recent years. Applications can be found in the domain of low-power design, optical computing, and quantum computing. In the past, several approaches have been introduced that synthesize reversible networks with respect to a given function. Most of these methods only approximate a… (More)

- Rolf Drechsler, Stephan Eggersglüß, +4 authors Daniel Tille
- IEEE Transactions on Computer-Aided Design of…
- 2008

Due to the rapidly growing size of integrated circuits, there is a need for new algorithms for automatic test pattern generation (ATPG). While classical algorithms reach their limit, there have been recent advances in algorithms to solve Boolean Satisfiability (SAT). Because Boolean SAT solvers are working on conjunctive normal forms (CNFs), the problem has… (More)

- Mathias Soeken, Stefan Frehse, Robert Wille, Rolf Drechsler
- Multiple-Valued Logic and Soft Computing
- 2012

It is a widely supported prediction that conventional computer hardware technologies are going to reach their limits in the near future. Thus, to further satisfy the needs for more computational power, alternatives are required that go beyond the scope of conventional technologies. Reversible logic marks a promising new direction where all operations are… (More)

- Rolf Drechsler, Detlef Sieling
- International Journal on Software Tools for…
- 2001

Decision diagrams (DDs) are the state-of-the-art data structure in VLSI CAD and have been successfully applied in many other fields. DDs are widely used and are also integrated in commercial tools. This special section comprises six contributed articles on various aspects of the theory and application of DDs. As preparation for these contributions, the… (More)

- Christoph Scholl, Rolf Drechsler, Bernd Becker
- 1997 Proceedings of IEEE International Conference…
- 1997

In many verification techniques fast functional evaluation of a Boolean network is needed. We investigate the idea of using Binary Decision Diagrams (BDDs) for functional simulation. The area-time trade-off that results from different minimization techniques of the BDD is discussed. We propose new minimization methods based on dynamic reordering that allow… (More)