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Predicated execution is an effective technique for dealing with conditional branches in application programs. However , there are several problems associated with conventional compiler support for predicated execution. First, all paths of control are combined into a single path regardless of their execution frequency and size with conventional if-conversion(More)
A compiler for VLIW and superscalar processors must expose sufficient instruction-level parallelism (ILP) to effectively utilize the parallel hardware. However, ILP within basic blocks is extremely limited for control-intensive programs. We have developed a set of techniques for exploiting ILP across basic block boundaries. These techniques are based on a(More)
Code optimization and scheduling for superscalar and superpipelined processors often increase the register requirement of programs. For existing instruction sets with a small to moderate number of registers, this increased register requirement can be a factor that limits the effectivess of the compiler. In this paper, we introduce a new architectural method(More)
Compiler-controlled speculative execution has been shown to be effective in increasing the available instruction levelparal-lelism (ILP) found in non-numeric programs. An important problem associated with compiler-controlled speculative execution is to accurately report and handle exceptions caused by speculatively executed instructions. Previous solutions(More)
Branch instructions are recognized as a major impediment to exploiting instruction level parallelism. Even with sophisticated branch prediction techniques, many frequently executed branches remain difficult to predict. An architecture supporting predicated execution may allow the compiler to remove many of these hard-to-predict branches, reducing the number(More)
Speculative execution is an important source of parallelism for VLIW and superscalar processors. A serious challenge with compiler-controlled speculative execution is to eeciently handle exceptions for speculative instructions. In this paper, a set of architectural features and compile-time scheduling support collectively referred to as sentinel scheduling(More)
Compile-time code transformations which expose instruction-level parallelism ILP typically take into account the constraints imposed b y a l l e x e cution scenarios in the program. However, there a r e additional opportunities to increase ILP along some execution sequences if the constraints from alternative execution sequences can be ignored.(More)
A compiler for VLIW and superscalar processors must expose suucient instruction-level parallelism ILP to eeectively utilize the parallel hardware. However, ILP within basic blocks is extremely limited for control-intensive programs. We h a v e developed a set of techniques for exploiting ILP across basic block boundaries. These techniques are based on a(More)
Predicated execution is an eeective technique for dealing with conditional branches in application programs. However , there are several problems associated with conventional compiler support for predicated execution. First, all paths of control are combined into a single path regardless of their execution frequency and size with conventional if-conversion(More)