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—This paper introduces the first comprehensive and accurate compact resistance–inductance–capacitance– conductance (RLCG) model for through-silicon vias (TSVs) in 3-D ICs valid from low-to high-frequency regimes, with consideration of the MOS effect in silicon, the alternating-current (ac) conduction in silicon, the skin effect in TSV metal, and the eddy(More)
A generalized impedance boundary condition is developed to rigorously model on-chip interconnects in the full-wave surface integral equation by a two-region formulation. It is a combination of the electric-field integral equation for the exterior region and the magnetic-field integral equation for the interior conductive region. The skin effect is,(More)
This paper examines the controversy between two approaches to inductance extraction: loop versus partial treatments for integrated circuit applications. We advocate the first one, and explicitly show that the alternative demands monopole-like magnetic configurations as well as dense inductance matrices. We argue that the uncertainties in the loop inductance(More)
With the onset of gigahertz frequencies on clocked digital systems, inductance effects become significant. We investigate appropriate regimes where signal propagation on an IC can be characterized as resulting from transmission line (TL) behavior. The signals propagate at a speed in the proximity of the speed of light in the medium. Our starting points are(More)
—Through-silicon vias (TSVs) in 3-D integrated circuits (ICs), which are used for connecting different active layers, introduce an important source of coupling noise arising from electrical coupling between TSVs and the active regions. This paper, for the first time, presents compact models based on a fully analytical approach for the electrical coupling(More)
We propose an efficient method to accurately compute the frequency-dependent impedance of VLSI interconnects in the presence of multilayer conductive substrates. The resulting accuracy (errors less than 3%) and CPU time reduction (more than an order of magnitude) emerge from three different ingredients: a 2-D Green's function approach with the correct(More)
We discuss interconnect parasitic extraction in the nanometer domain using the ITRS 2005 roadmap for future technology generations. Resistance becomes the dominant contribution for timing for local wires at 65 nm and beyond, a major qualitative change. For scaled wires, maintaining global wire routes within 1 clock period is expensive in terms of power(More)
We present a gridless method for solving the interior problem for a set of conductors in an homogeneous dielectric, at sufficiently high frequencies, valid for conductor lengths that are not small compared to the minimum wavelength, and transverse dimensions that are large compared to the skin depth. For IC applications, we cover the regime 10--100 GHz and(More)