Roberto A. Hexsel

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We describe the design and VHDL implementation of a cache coherent MPSoC named Minimalist Cache Coherent MPSoC (MCCM). The system comprises 1 to 8 MIPS-I processors, coherent primary data caches, memory management units, memory controller and the interconnection. We present a detailed account of the implementation, focusing on the shared memory subsystem. A(More)
In this paper we present a real-time tracking system of surgical instruments in laparoscopic operations. We combine Condensation tracking, with the Hough Transform in order to obtain an efficient and accurate tracking. The Condensation algorithm performs well in heavy clutter, and the Hough Transform is robust under illumination changes, occlusion and(More)
—This paper presents an efficient IrisCode classifier, built from phase features which uses AdaBoost for the selection of Gabor wavelets bandwidths. The final iris classifier consists of a weighted contribution of weak classifiers. As weak clas-sifiers we use 3-split decision trees that identify a candidate based on the Levenshtein distance between phase(More)
In this paper we explore the design space of data caches looking for the combinations of design parameters that produce the best results at the smallest sizes. We introduce a technique named Pollution Control Victim Cache (PCVC) which improves the Pollution Control Cache (PCC), is simpler and performs better. Our simulations were run on the SimpleScalar(More)
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