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—Computer-aided design (CAD) techniques are absolutely essential to harness the ever-increasing complexity of the microsystem design. Similarly, the technology CAD (TCAD) tools played a key role in the development of new technology generations. Although there is a common belief that the TCAD tools have been trailing the technology development, the situation(More)
This paper presents a compact direct tunneling current model for circuit simulation to predict ultra-thin gate oxide (2.0 nm) CMOS circuit performance by introducing the explicit surface potential model and quantum-mechanical corrections. It demonstrates good agreements with the results from the numerical solver and measured data for the very-thin gate(More)
A density-gradient (DG) model is used to calculate quantum-mechanical corrections to classical carrier transport in MOS in-version/accumulation layers. The model is compared to measured data and to a fully self-consistent coupled Schrr odinger and Pois-son equation (SCSP) solver. Good agreement is demonstrated for MOS capacitors with gate oxide as thin as(More)
– The practical design issues of an electrostatic micromechanical actuator that can travel beyond the trademark limit of conventional actuators are presented. The actuator employs a series capacitor to extend the effective electrical gap of the device and to provide stabilizing negative feedback. Sources of parasitics – from layout and from 2-D non-uniform(More)
We present a framework and control policies for optimizing dynamic control of various self-tuning parameters over lifetime in the presence of circuit aging. Our framework introduces dynamic cooling as one of the self-tuning parameters, in addition to supply voltage and clock frequency. Our optimized self-tuning satisfies performance constraints at all times(More)
On-Chip inductance modeling of VLSI interconnects is presented which captures 3D geometry from layout design and process technology information. Analytical formulae are derived for quick and accurate inductance estimation which can be used in circuit simulations and whole chip extraction screening process. Circuit simulations show critical global wire(More)
—The physical origin of the excess thermal noise in short channel MOSFETs is explained based on numerical noise simulation. The impedance field representation and extraction method demonstrate that the drain current noise is dominated by source side contributions. Analysis identifies local ac channel resistance variations as the primary controlling factor.(More)
A methodology for handling a class of stiff multiparticle parabolic PDE's in one and two dimensions is presented. The particular example considered in this work is the interaction and diffusion of two point defects in silicon, interstitials and vacancies. Newton's method, latency techniques, and second-order time-stepping approaches all contribute in(More)