Robert Schwencker

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We present a new method for mismatch analysis and automatic yield optimization of analog integrated circuits with respect to global, local and operational tolerances. Effectiveness and efficiency of yield estimation and optimization are guaranteed by consideration of feasibility regions and by performance linearization at worst-case points. The proposed(More)
In this paper, a new method for analog circuit sizing with respect to manufacturing and operating tolerances is presented. Two types of robustness objectives are presented, i.e. parameter distances for the nominal design and worstcase distances for the design centering. Moreover, the generalized boundary curve is presented as a method to determine a(More)
Virtual Prototypes (VPs) based on Transaction Level Modeling (TLM) have become a de-facto standard in today's SoC design, enabling early SW development. However, due to the growing complexity of SoC architectures full system simulations (HW+SW) become a bottleneck reducing this benefit. Hence, it is necessary to develop modeling styles which allow for(More)
In this paper, a method for nominal design of analog integrated circuits is presented that includes process variations and operating ranges by worst-case parameter sets.These sets are calculated adaptively during the sizing process based on sensitivity analyses. The method leads to robust designs with high parametric yield, while being muchmore efficient(More)
In this paper a method for the automatic sizing of analog integrated circuits is presented. Basic sizing rules, representing circuit knowledge, are set up before the sizing and are introduced as structural constraints into the sizing process. Systematic consideration of these structural constraints during the automatic sizing prevents pathologically sized(More)
In this report a method for the design centering of analog circuits, based on worstcase distances (WCD) is presented. In order to keep the linearization error small, only the WCDs and not the strongly nonlinear objective function itself is linearized. For the resulting nonlinear trust-region problem the generalized boundary curve (GBC) is derived as a(More)
In this paper, an industrial application of symbolic modeling methods to the design of interface circuits is presented. A modeling method based on circuit knowledge and performance-oriented error estimation is used for an automatic generation of analog behavioral models. Results calculated with an output buffer show the effectiveness of this approach.
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