Robert Rutten

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In this paper, a high-speed continuous-time (CT) ΔΣ ADC topology is proposed that absorbs the pole normally caused by the quantizer’s input capacitance, while a local feedback loop compensates for the quantizer’s excess delay. These measures allow a high-resolution multi-bit ΔΣ ADC to operate at GHz sampling rates. The bandwidth of this CMOS ΔΣ ADC is 6×(More)
In this paper we analyze the architecture of a 13 bits 4.096 GHz multi-stage decimation filter for multistandard radio receivers. It also explores the benefits of Carry-Save format numbers in this decimation filter. After trading off between area and power consumption, we propose to use shift-and-adder for high data rate decimation stages and hardware(More)