Robert Rogenmoser

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The performance of a CMOS circuit depends heavily on its transistor sizes. We have tested a standard optimizer, a Monte Carlo scheme and a method based on Genetic Algorithms combined with very accurate SPICE simulations to automatically optimize transistor sizes of three diierent digital CMOS circuits. While the standard optimizer and the Monte Carlo scheme(More)
65nm Deeply Depleted Channel (DDC TM) transistors have been fabricated with a halo-free, un-doped epitaxial channel and enable reduced threshold voltage (V T) variation, lower supply voltage (V CC), enhanced body effect and I EFF. Digital circuits made using this technology show benefits ranging from 47% power reduction to 38% frequency increase. Analog(More)
Transistor size optimization is one method to reduce the power dissipation of CMOS VLSI circuits. Analysis shows that parasitic capacitances and velocity saturation of submicron technologies favor wider than minimum transistor sizes. The reason is that they allow for a larger reduction of the supply voltage which results in more substantial power savings.(More)
A process monitor based on slew-rate measurement has been applied to a body bias control system to detect the process corners and adjust the body bias voltage necessary to meet the power and performance requirements for CMOS circuits. The process monitor consists of N- and P- type slew generators, pulse generator, pulse extender, counter and control(More)
A unique LVS (layout-versus-schematic) methodology has been developed for the verification of a four-core microprocessor with multiple power domains using a triple-well 90-nm CMOS technology. The chip is migrated from its previous generation that is for a twin-well process. Due to the design reuse, VDD and GND are designed as global nets but they are not(More)
An SoC with ARM&#x00AE; Cortex&#x2122;-M0 CPU cores and SRAMs is implemented in both 65nm baseline and Deeply Depleted Channel&#x2122; (DDC) technologies. DDC technology demonstrates more than 50% active and static power reduction for the CPU cores at matched 350 MHz speed via V<sub>DD</sub> scaling and body biasing. Alternatively DDC technology(More)
— An SoC with ARM® Cortex™-M0 CPU cores and SRAMs is implemented in both 65nm baseline and Deeply Depleted Channel™ (DDC) technologies. DDC technology demonstrates more than 50% active and static power reduction for the CPU cores at matched 350 MHz speed via V DD scaling and body biasing. Alternatively, DDC technology demonstrates 35% speed increase at(More)
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