Robert R. Henry

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1 Overview BURG is a program that generates a fast tree parser using BURS (Bottom-Up Rewrite System) technology. It accepts a cost-augmented tree grammar and emits a C program that discovers in linear time an optimal parse of trees in the language described by the grammar. BURG has been used to construct fast optimal instruction selectors for use in code(More)
The University of Washington illustrating compiler (UWPI) automatically illustrates the data structures used in simple programs written in a subset of Pascal<supscrpt>2</supscrpt>. A UWPI user submits a program to UWPI, and can then watch a graphical display show time varying illustrations of the data structures and program source code. UWPI uses the(More)
To achieve high performance in uniprocessor RISC systems, compilers must perform both register allocation to reduce memory references and instruction scheduling to avoid pipeline hazards. Compilers that separate the two functions should perform poorly on uniprocessor RISCS that support multi-cycle operations, particularly on computation-intensive workloads.(More)
Marion is a retargetable code generator system designed specifically for RISCS. Each code generator is built from a machine description that includes code selection and code scheduling information in a concise and readable format. The description language is designed to be easy to use, yet rich enough to support a broad range of RISCS. We have used Marion(More)
We have constructed a local code generator for the VAX-11<supscrpt>2</supscrpt> using a parser-like instruction pattern matcher. The code generator replaces the second pass of the UNIX<supscrpt>3</supscrpt> Portable &#8220;Crdquo; compiler. This paper describes the design of the code generator and the special considerations imposed by the pattern matching(More)
SUMMARY Code generators based on bottom-up rewrite systems (BURS) are automatically generated from machine-description grammars. They produce locally optimal code for expression trees, but their tables are large and require compile-time interpretation. This paper describes a program that compiles BURS tables into a combination of hard code and data.(More)
This paper examines the effect of code generation strategy and register set size and structure on the performance of RISC processors. We vary the number of registers from 16 to 128, in both split and shared organizations , and use three different code generation strategies that differ in the way their instruction schedulers and register allocators cooperate(More)