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This paper presents the impact of multiple-detect test patterns on outgoing product quality. It introduces an ATPG tool that generates multiple-detect test patterns while maximizing the coverage of node-to-node bridging defects. Volume data obtained by testing a production ASIC with these new multiple-detect patterns shows increased defect screening(More)
Maintaining product quality at reasonable test cost in very deep sub-micron process has become a major challenge especially due to multiple manufacturing locations with varying defect and parametric distributions. Increasing vector counts and binary search routines are now necessary for subtle defect screening. In addition, parametric tests and at-spec(More)
The subject of this paper is variance reduction and Nearest Neighbor Residual estimates for I DDQ and other continuous-valued test measurements. The key, new concept introduced is data-driven neighborhood identification about a die to reduce the variance of good and faulty I DDQ distributions. Using LSI Logic production data, neighborhood selection(More)
In sub-micron CMOS processes, it has become increasingly difficult to identify and separate outliers from the intrinsic distribution at test. This is due to the increasing inadequacy of reliability screens such as burn-in and IDDQ testing. Statistical Post-Processing (SPP) methods have been developed to run off-tester using the raw data generated from(More)
Transition delay fault (TDF) testing has become a necessary test method in very deep sub micron (VDSM) technologies due to the presence of resistive defects that cause subtle timing failures. The transition delay fault model is based on a slow-to-rise and slow-to-fall fault at each node in the circuit. Some resistive defects such as resistive vias actually(More)