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This work explores the feasibility of implementing a floating-point exponentiation unit on reconfigurable computing systems. A table-driven exponentiation unit was implemented using synthesizable VHDL. The project included creating pipelined submodules for implementing basic IEEE-754 single precision operations such as addition, multiplication, and division(More)
This work explores the feasibility of implementing a floating-point exponentiation unit on reconfigurable computing systems. A table-driven exponentiation unit was implemented using synthesizable VHDL. The hardware implementation was performed using the same methodology as Bui et. al. We first implemented the individual components required to perform the(More)
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