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- Kanwar Jit Singh, Luciano Lavagno, +5 authors Robert K. Brayton
- 2004

Sis is an interactive tool for synthesis andoptimization of sequential circuits. Given a state transition table, a signal transition graph, oralogic-level description of asequentialcircuit, itâ€¦ (More)

We present a logical formalism for expressing properties of continuous time Markov chains. The semantics for such properties arise as a natural extension of previous work on discrete time Markovâ€¦ (More)

- Robert K. Brayton, Alan Mishchenko
- CAV
- 2010

ABC is a public-domain system for logic synthesis and formal verification of binary logic circuits appearing in synchronous hardware designs. ABC combines scalable logic transformations based onâ€¦ (More)

SIS i.s ni i i i i t e r a c t i r ~ c tool for syii thcsis arid o p t i i i i c a tioii of . scquc i i t i a l circii i ts . (,'iiscii n s fn t c t m i i s i t i o i i ta1116 or a log icl sue lâ€¦ (More)

- Robert K. Brayton, Gary D. Hachtel, +13 authors Tiziano Villa
- CAV
- 1996

ion Manual abstraction can be performed by giving a file containing the names of variables to abstract. For each variable appearing in the file, a new primary input node is created to drive all theâ€¦ (More)

- Robert K. Brayton, Richard L. Rudell, Alberto L. Sangiovanni-Vincentelli, Albert R. Wang
- IEEE Transactions on Computer-Aided Design ofâ€¦
- 1987

MIS is both an interactive and a batch-oriented multilevel logic synthesis and minimization system. MIS starts from the combinational logic extracted, typically, from a high-level description of aâ€¦ (More)

- Paul R. Stephan, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
- IEEE Trans. on CAD of Integrated Circuits andâ€¦
- 1996

Wepresenta new algorithmforcombinationaltestgenerationwhichimproveson Larrabee's resultsby usingmore robust and simpler heuristics. In TEGUS, test generation using satisfiability, the characteristicâ€¦ (More)

- Niklas EÃ©n, Alan Mishchenko, Robert K. Brayton
- 2011 Formal Methods in Computer-Aided Designâ€¦
- 2011

Last spring, in March 2010, Aaron Bradley published the first truly new bit-level symbolic model checking algorithm since Ken McMillan's interpolation based model checking procedure introduced inâ€¦ (More)

- Alan Mishchenko, Satrajit Chatterjee, Robert K. Brayton
- 2006 43rd ACM/IEEE Design Automation Conference
- 2006

This paper presents a technique for preprocessing combinational logic before technology mapping. The technique is based on the representation of combinational logic using And-Inverter Graphs (AIGs),â€¦ (More)

- Arvind Srinivasan, Timothy Kam, Sharad Malik, Robert K. Brayton
- ICCAD
- 1990