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- Ellen M. Sentovich, Kanwar Jit Singh, +6 authors Alberto Sangiovanni-Vincentelli
- 1992

SIS is an interactive tool for synthesis and optimization of sequential circuits. Given a state transition table, a signal transition graph, or a logic-level description of a sequential circuit, it produces an optimized net-list in the target technology while preserving the sequential input-output behavior. Many different programs and algorithms have been… (More)

We present a logical formalism for expressing properties of continuous time Markov chains. The semantics for such properties arise as a natural extension of previous work on discrete time Markov chains to continuous time. The major result is that the veriication problem is decidable; this is shown using results in algebraic and transcendental number theory.

- Robert K. Brayton, Gary D. Hachtel, +13 authors Tiziano Villa
- CAV
- 1996

ion Manual abstraction can be performed by giving a file containing the names of variables to abstract. For each variable appearing in the file, a new primary input node is created to drive all the nodes that were previously driven by the variable. Abstracting a net effectively allows it to take any value in its range, at every clock cycle. Fair CTL model… (More)

- Robert K. Brayton, Richard L. Rudell, Alberto L. Sangiovanni-Vincentelli, Albert R. Wang
- IEEE Transactions on Computer-Aided Design of…
- 1987

MIS is both an interactive and a batch-oriented multilevel logic synthesis and minimization system. MIS starts from the combinational logic extracted, typically, from a high-level description of a macrocell. It produces a multilevel set of optimized logic equations preserving the input-output behavior. The system includes both fast and slower (but more… (More)

- Paul R. Stephan, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
- IEEE Trans. on CAD of Integrated Circuits and…
- 1996

We present a robust and efficient algorithm for combinational test generation using a reduction to satisfiability (SAT). The algorithm, TEGUS, has the following features. We choose a form for the test set characteristic equation which minimizes its size. The simplified equation is solved by an algorithm for SAT using simple, but powerful, greedy heuristics,… (More)

- Robert K. Brayton, Alan Mishchenko
- CAV
- 2010

ABC is a public-domain system for logic synthesis and formal verification of binary logic circuits appearing in synchronous hardware designs. ABC combines scalable logic transformations based on And-Inverter Graphs (AIGs), with a variety of innovative algorithms. A focus on the synergy of sequential synthesis and sequential verification leads to… (More)

- Niklas Eén, Alan Mishchenko, Robert K. Brayton
- FMCAD
- 2011

Last spring, in March 2010, Aaron Bradley published the first truly new bit-level symbolic model checking algorithm since Ken McMillan’s interpolation based model checking procedure introduced in 2003. Our experience with the algorithm suggests that it is stronger than interpolation on industrial problems, and that it is an important algorithm to study… (More)

- Arvind Srinivasan, Timothy Kam, Sharad Malik, Robert K. Brayton
- ICCAD
- 1990

- Alan Mishchenko, Satrajit Chatterjee, Robert K. Brayton
- 2006 43rd ACM/IEEE Design Automation Conference
- 2006

This paper presents a technique for preprocessing combinational logic before technology mapping. The technique is based on the representation of combinational logic using And-Inverter Graphs (AIGs), a networks of two-input ANDs and inverters. The optimization works by alternating DAG-aware AIG rewriting, which reduces area by sharing common logic without… (More)