Robert F. Molyneaux

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INTERNATIONAL TEST CONFERENCE 1 1-4244-1128-9/07/$25.00 © 2007 IEEE Abstract The Niagara2 System-on-Chip is SUN Microsystem’s latest processor in the Eco-sensitive CoolThreads line of multi-threaded servers. This DFT survey of the Niagara2 chip introduces the RAWWCas memory test, a Hybrid Flop Design and a fast efficient bitmapping architecture called DMO.(More)
ing force for needing better and faster, debug capabilities. We are truly building systems on a chip, board level interfaces which could previously be monitored and debugged with logic analyzers are now buried on silicon. We need to consider burying the logic analyzers along with the interfaces. The debug task is sometimes made more difficult in today’s(More)
This paper describes the use of a high-level view (functionalview) of a clock regenerator circuit for generating effective andinexpensive manufacturing tests. It is shown that the tests generatedfrom the traditional, structural view add hardwareoverhead, increase design time and potentially lower effectiveyield when compared to the tests generated from the(More)
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