Robert A. Groves

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—A wide-band physical and scalable 2-5 equivalent circuit model for on-chip spiral inductors is developed. Based on physical derivation and circuit theory, closed-form formulas are generated to calculate the RLC circuit elements directly from the inductor layout. The 2-5 model accurately captures () and () characteristics beyond the self-resonant frequency.(More)
Foundation of rf CMOS and SiGe BiCMOS technologies This paper provides a detailed description of the IBM SiGe BiCMOS and rf CMOS technologies. The technologies provide high-performance SiGe heterojunction bipolar transistors (HBTs) combined with advanced CMOS technology and a variety of passive devices critical for realizing an integrated mixed-signal(More)
—The radio-frequency (rf) performance of a 0.18-m CMOS logic technology is assessed by evaluating the cutoff and maximum oscillation frequencies (and max) the minimum noise figure (min) and associated power gain () and the 1/-noise of the devices. Gate-biasing and channel-length and gate-finger-length adjustments are identified as means to optimize the rf(More)
This paper expands the on-chip interconnect-aware methodology for high-speed analog and mixed signal design, presented in [4], into a wider class of designs, including dense layout CMOS design. The proposed solution employs a set of parameterized on-chip transmission line (T line) devices for the critical interconnects, which is expanded to include coplanar(More)
—This paper demonstrates a predictive noise parameter estimation methodology for UHV/CVD SiGe HBT's which combines ac measurement, calibrated ac simulation and two of the latest Y-parameter-based noise models: 1) the thermody-namic noise model, and 2) the SPICE noise model. The bias current and frequency dependence of the minimum noise figure, the optimum(More)
Design automation methodology and rf/analog modeling for rf CMOS and SiGe BiCMOS technologies The rapidly expanding telecommunications market has led to a need for advanced rf integrated circuits. Complex rf-and mixed-signal system-on-chip designs require accurate prediction early in the design schedule, and time-to-market pressures dictate that design(More)
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