Rob Fanfelle

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Simulations indicate a simple modification of existing virtual memory hardware can significantly reduce the number of pins required to transmit address information from processor to off-chip memory. This modification consists of partitioning a TLB so that virtual page numbers are stored in a cache on the processor and corresponding real page numbers are(More)
This paper presents a simple modification of a computing system’s virtual memory hardware that can sharply reduce the number of pins required to transmit address information between a single chip processor and off-chip memory. By partitioning the virtual memory system’s translation lookaside buffer (TLB) so that the virtual page numbers are stored in a(More)
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