Rinaldo Castello

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An algorithmic analog-to-digital conversion technique is described which is capable of achieving high-resolution conversion without the use of matched capacitors in an MOS technology. The exact integral multiplication of the signal required by the conversion is realized through an algorithmic circuit method which involves charge summing with an MOS(More)
A two-dimensions Vernier algorithm applied to a time to digital converter (TDC) is presented. The solution proposed minimizes the length of the delay lines used to perform the digital conversion leading to a better efficiency compared to traditional linear approaches. A 7-bits TDC prototype, targeted for all digital PLL application, was realized in 65 nm(More)
A direct conversion 802.11a receiver front-end including a synthesizer with quadrature VCO has been integrated in a 0.13-/spl mu/m CMOS process. The chip has an active area of 1.8 mm/sup 2/ with the entire RF portion operated from 1.2 V and the low frequency portion operated from 2.5 V. Its key features are a current driven passive mixer with a low(More)
A /spl Sigma//spl Delta/ fractional-N frequency synthesizer targeting WCDMA receiver specifications is presented. Through spurs compensation and linearization techniques, the PLL bandwidth is significantly extended with only a slight increase in the integrated phase noise. In a 0.18-/spl mu/m standard digital CMOS technology a fully integrated prototype(More)
The switched-capacitor technique which implements analog functions in CMOS technology requires capacitors, switches, and opamps. Supply voltage reduction does not affect capacitors. On the other hand, turning MOS switches on and off and maintaining proper opamp operation are difficult with reduced supply voltage. Reducing the supply voltage reduces MOS(More)
This paper presents a fully integrated CMOS receiver front-end based on a direct conversion architecture for UMTS/802.11b-g and a low-IF architecture at 100 kHz for DCS1800. The two key building blocks are a multiband low-noise amplifier (LNA) that uses positive feedback to improve its gain and a highly linear mixer. The front-end, integrated in a 0.13 /spl(More)
A multistandard SAW-less receiver is designed exploring a current-mode architecture. A class-AB common-gate transformer-based low-noise transconductor amplifier (LNTA) is used to provide high linearity and harmonic filtering. A resonant passive mixer is adopted in order to allow the current-mode operation and improve the harmonic rejection. A low-power(More)
This paper presents the first quadrature RF receiver front-end where, in a single stage, low-noise amplifier (LNA), mixer and voltage-controlled oscillator (VCO) share the same bias current. The new structure exploits the intrinsic mixing functionality of a classical LC tank oscillator providing a compact and low-power solution compatible with low-voltage(More)
An intuitive yet sufficiently accurate formulation of the phase noise of various commonly used oscillators, including most types of class-B (standard, AC-coupled and with tail filter) and class-C, is derived and used to compare their fundamental limitations. A noise factor that represents the difference between the maximum achievable Figure of Merit and the(More)
A description is given of a high-performance fifth-order low-pass switched-capacitor filter operating form a single 5-V supply. The filter uses a fully differential topology combined with input-to-output class AB amplifier design, dynamic biasing, and switched-capacitor common-mode feedback. An experimental prototype fabricated in a 5-/spl mu/m CMOS(More)