Rimantas Seinauskas

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The design complexity of systems on a chip drives the need to reuse legacy or intellectual property cores, whose gate-level implementation details are unavailable. In this paper we consider the realization-independent testing and the impact of circuit realization on the fault coverage. We investigated two fault models (input-output pin pair fault and(More)
The paper presents two functional fault models that are devoted for functional delay test generation for non-scan synchronous sequential circuits. These fault models form one joint functional fault model. The non-scan sequential circuit is represented as the iterative logic array model consisting of k copies of the combinational logic of the circuit. The(More)
Rapid advances of semiconductor technology lead to higher circuit integration as well as higher operating frequencies. The statistical variations of the parameters during the manufacturing process as well as physical defects in integrated circuits can sometimes degrade circuit performance without altering its logic functionality. These faults are called(More)
The test can be developed at the functional level of the circuit. Such an approach allows developing the test at the early stages of the design process in parallel with other activities of this process. The problem is to choose the right fault model because the implementation of the circuit is not available yet. The paper introduces three new fault models(More)
The design complexity of systems on a chip drives the need to reuse legacy or intellectual property cores, whose gate-level implementation details are unavailable. The core test depends on manufacturing technologies and changes permanently during a design lifecycle. In this paper we consider the impact of circuit realization on the fault coverage of the(More)
The quality of delay testing focused on small delay defects is not known when transition fault model is used. The paper presents a method that evaluates the quality of the delay test according to the covered paths of the circuit and constructs the paths, which could be used as the input to the path delay test generator. All the constructed paths are(More)
The testing phase is becoming the most crucial part of the overall design process, which delays the time-to-market of the digital devices. In order to reduce the complexity of test generation and to decrease the time-to-market, one needs to begin the test design at higher levels of abstraction. In this paper a new approach for functional delay test(More)