Rimantas Seinauskas

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The design complexity of systems on a chip drives the need to reuse legacy or intellectual property cores, whose gate-level implementation details are unavailable. In this paper we consider the realization-independent testing and the impact of circuit realization on the fault coverage. We investigated two fault models (input-output pin pair fault and(More)
Identifying legal and illegal states significantly reduces computational complexity of ATPG. A unified framework for identification of the legal and illegal states is presented. Most known methods for identification of the legal and illegal states are interpretable within this framework. New theorems and the resulting procedures for identifying exact(More)
The same circuit may be described at algorithmic, behavioral or gate level. Test generation is usually performed for every level separately. We introduce a test generation approach based on test selection by means of simulation at algorithmic level of circuit description. The generated test could be applied to VHDL behavioral level as test bench. This test(More)
The paper presents functional delay test generation approach for non-scan synchronous sequential circuits. The non-scan sequential circuit is represented as the iterative logic array model consisting of k copies of the combinational logic of the circuit. The value k defines the number of clock cycles. The software prototype model is used for the(More)