Rimantas Seinauskas

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The paper presents two functional fault models that are devoted for functional delay test generation for non-scan synchronous sequential circuits. These fault models form one joint functional fault model. The non-scan sequential circuit is represented as the iterative logic array model consisting of k copies of the combinational logic of the circuit. The(More)
Rapid advances of semiconductor technology lead to higher circuit integration as well as higher operating frequencies. The statistical variations of the parameters during the manufacturing process as well as physical defects in integrated circuits can sometimes degrade circuit performance without altering its logic functionality. These faults are called(More)
The paper investigates the possibilities of application of random generated test sequences for at-speed testing of non-scan synchronous sequential circuits. Our research shows that relatively long random test sequences exhibit better transition fault coverages than tests produced by deterministic ATPG tools. We proposed an approach for dividing of long test(More)
Rapid advances of semiconductor technology lead to higher circuit integration as well as higher operating frequencies. Conventional fault models like the standard single stuck-at model were developed for gate-level logic circuits. Regardless of stuck-at fault model's efficiency for several decades, alternative models need to account for deep sub-micron(More)
The design complexity of systems on a chip drives the need to reuse legacy or intellectual property cores, whose gate-level implementation details are unavailable. In this paper we consider the realization-independent testing and the impact of circuit realization on the fault coverage. We investigated two fault models (input-output pin pair fault and(More)
The test can be developed at the functional level of the circuit. Such an approach allows developing the test at the early stages of the design process in parallel with other activities of this process. The problem is to choose the right fault model because the implementation of the circuit is not available yet. The paper introduces three new fault models(More)
The same circuit may be described at algorithmic, behavioral or gate level. Test generation is usually performed for every level separately. We introduce a test generation approach based on test selection by means of simulation at algorithmic level of circuit description. The generated test could be applied to VHDL behavioral level as test bench. This test(More)