Richard Hagelauer

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A single-chip, fully-integrated 3G UMTS/W-CDMA transceiver has been implemented in a standard 75-GHz/0.35 /spl mu/m SiGe BiCMOS process for use in FDD mobile terminals. The design comprises two integer-N/fractional-N synthesizers with fully integrated CMOS VCOs, on-chip tuning and PLL, a zero-IF receiver and a direct-conversion transmitter. The zero-IF(More)
A zero-IF receiver for UMTS realized by using an advanced 0.35 /spl mu/m SiGe BiCMOS process with 75 GHz transit frequency is presented. The focal point is the analog baseband chain consisting of a low-noise buffer (LNB), a fully integrated channel selection filter, programmable gain amplifiers (PGA) and circuits to reduce the effects of DC-offsets. The(More)
A fully integrated Si bipolar IF-receiver and IF-transmitter with on-chip synthesizer for use in third-generation variable duplex W-CDMA mobiles is introduced. Both devices incorporate an IF-synthesizer with on-chip VCO tuning and tank as well as 5th order baseband filters and comply with ARIB W-CDMA and UMTS standards. The devices are mounted in a small(More)
In this paper, we present a methodology to establish an accurate and power-aware simulation of wireless sensor networks. As the design of software applications running on resource-constrained sensor nodes mainly influences both timing and power consumption in the network, it is crucial to include these components in the simulation. Besides considering the(More)
– The software-defined-radio concept received increasing attention due to necessity of multi-mode/multi-system capable terminals for next generation communication systems. This paper summarizes the requirements of a multi-mode compliant digital-front-end (DFE) and describes concepts for cellular terminal implementations on silicon. A partitioning is(More)
A key property of polar modulator systems is the matching between amplitude and phase path. This paper shows how mismatches between these paths degrade performance and introduce difficulties in designing GSM EDGE systems. A transmitter overcoming these problems is presented. The chip has been implemented in a 0.13μm CMOS technology, with a nominal margin of(More)
After a decade of research in the field of wireless sensor networks the energy consumption remains the dominating constraint. Complex algorithms with non-negligible runtimes must be processed by resource-limited nodes, and therefore require in-depth knowledge of the temporal behavior of the software and hardware components. However, state-of-the-art(More)