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We present a single-chip array of 100 biologically-based electronic neuron models interconnected to each other and the outside environment through 30,000 synapses. The chip was fabricated in a standard 350 nm CMOS IC process. Our approach used dense circuit models of synaptic behavior, including biological computation and learning, as well as transistor(More)
We describe a novel neuromorphic chip architecture that models neurons for efficient computation. Traditional architectures of neuron array chips consist of large scale systems that are interfaced with AER for implementing intra- or inter-chip connectivity. We present a chip that uses AER for inter-chip communication but uses fast, reconfigurable FPGA-style(More)
— This paper presents a floating-gate (FG)-based, field-programmable analog array (FPAA) system-on-chip (SoC) that integrates analog and digital programmable and config-urable blocks with a 16-bit open-source MSP430 microprocessor (µP) and resulting interface circuitry. We show the FPAA SoC architecture, experimental results from a range of circuits(More)
OVERVIEW This body of work as whole has the theme of using floating-gates and reconfigurable systems to explore and implement non-traditional computing solutions to difficult problems. Various computational methodologies are used simultaneously to solve problems by mapping pieces of them to the appropriate type of computer. There exists no systematic(More)
ACKNOWLEDGMENTS I would like to thank my advisor, Dr. Paul Hasler, for giving me the flexibility to persue this topic, and for his patience while doing so. Figure 2 Input and output voltage transients of a CMOS gate driving a CMOS gate, shown are the measurements of rising propagation delay, d r , and output fall time, t f. . Figure 5 Transient voltages and(More)
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