Richard B. Wunderlich

Learn More
We present a single-chip array of 100 biologically-based electronic neuron models interconnected to each other and the outside environment through 30,000 synapses. The chip was fabricated in a standard 350 nm CMOS IC process. Our approach used dense circuit models of synaptic behavior, including biological computation and learning, as well as transistor(More)
We describe a novel neuromorphic chip architecture that models neurons for efficient computation. Traditional architectures of neuron array chips consist of large scale systems that are interfaced with AER for implementing intra- or inter-chip connectivity. We present a chip that uses AER for inter-chip communication but uses fast, reconfigurable FPGA-style(More)
The authors present a Floating-Gate based, System-On-Chip large-scale Field-Programmable Analog Array IC that integrates divergent concepts from previous designs along with low-power digital computation including a 16bit open-source MSP430 microprocessor, and resulting interface circuitry such as DACs and ADCs. We describe the SoC FPAA architecture,(More)
  • 1