Learn More
To cope with the problem of instability and imperfect reverse isolation, a millimeter-wave voltage-voltage transformer feedback low noise amplifier has been analyzed, designed, and measured in CMOS 65 nm technology. Analytical formulae are derived for describing the stability, gain, and noise in this circuit topology. An analogy with the classic concept of(More)
This paper presents a broadband, static, 2:1 frequency divider in a bulk 90 nm CMOS LP (low-power) technology with maximum operating frequency of 35.5 GHz. The divider exhibits an enhanced input sensitivity, below 0 dBm, over a broad input range of 31 GHz and consumes 24 mA from a 1.2 V supply. The phase noise of the divider is -124.6 dBc/Hz at 1 MHz offset(More)
This paper describes a fully integrated differential power amplifier (PA) operating at 60 GHz ISM band and implemented in 45nm CMOS technology. The PA is based on a distributed active transformer (DAT) topology which enables simultaneous power combining and realization of an efficient impedance matching. To cope with the asymmetric nature of DAT, resulting(More)
This paper presents the analysis of the performance of charge pump, and the design strategy and efficiency optimization of 2.4GHz micro-power charge pump using 65nm CMOS technology. The model of the charge pump takes account of the threshold voltage variation, bulk modulation, and the major parasitic capacitor. Charge pump is sensitive to the input voltage(More)
A fully integrated 2-channel Ka-band True Time Delay (TTD) phase shifter with 12ps continuous changing delay time has been realized in a 0.25μm SiGe:C BiCMOS technology. A delay variation cancellation technique is proposed, resulting in less than 0.8ps delay variation over a 20-40GHz frequency span, meanwhile maintaining a constant input impedance.(More)
A fully differential 60 GHz down-converter in 65-nm CMOS technology is presented. The circuit, including the buffers, draws 5 mA from a 1.2 V supply. The measured power conversion gain is 4 dB with an IF 3 dB bandwidth of 1.3 GHz. Measured IIP2 and IIP3 are 16.6 and −6 dBm respectively. The mixer will be part of a 60 GHz receiver.
This paper presents a low power, low phase noise mm-wave voltage controlled oscillator. The VCO can be tuned from 41 to 44.5 GHz (8% tuning range) and utilizes a differential tuning mechanism based on varactors and fixed MIM capacitors. Fabricated in a bulk CMOS 65 nm technology, it consumes 3.6 mW and exhibits a phase noise of -106 dBc/Hz at 1 MHz offset(More)
This paper presents a two-stage fully integrated 60 GHz differential Low Noise Amplifier implemented in a TSMC bulk CMOS 65 nm technology. Implementation of a voltage-voltage feedback enables the neutralization of the Miller capacitance and the achievement of flat gain with a deviation of ± 0.25 dB over the entire 6 GHz bandwidth. It features a(More)