Rex Berridge

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model Transistor-level VIM parasitic netlist Schematic, netlist Complete layout IBM J. RES. & DEV. VOL. 51 NO. 6 NOVEMBER 2007 R. BERRIDGE ET AL. 687 technology-specific wire models into the schematic netlist. Among the more accurately placed models in netlist, downstream analysis tools were more effective. Circuit optimization The IBM EinsTuner circuit(More)
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