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I t is well recognized that there is a strong correlation between traffic congestion and air quality, especially in dense urban areas. Vehicles idling in queue significantly contribute to the pollutant emission problems experienced in many major metropolitan areas. Consequently, strategies to improve traffic operations can yield important improvements in(More)
This paper presents the design and performance of a phase-locked-loop (PLL) clock synthesizer for low-jitter clock synthesizer applications. This product operates in the range of 100 MHz to 700 MHz with very low phase noise and low-voltage-differential-signal (LVDS) outputs. The design focuses on the minimization of the phase noise, or timing jitter, of the(More)
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