Reto Da Forno

Learn More
The wireless sensor network community is currently undergoing a platform paradigm shift, moving away from classical single-processor motes toward heterogeneous multi-processor architectures. These emerging platforms promise efficient concurrent processing with energy-proportional system performance. The use of shared interconnects and shared memory for(More)
We present the design of a reliable nurse call system based on wireless embedded devices and multi-hop protocols. Our work is motivated by the need for such system during annual summer camps for people with muscular dystrophy and the lack of suitable alternative solutions. We describe how our prototype meets the reliability and real-time requirements of(More)
We demonstrate the capabilities of Bolt, an ultra-low-power processor interconnect for the composable construction of new multi-processor wireless embedded platforms. Bolt provides asynchronous bidirectional communication between two processors with predictable message transfer times. In this way, Bolt solves the resource interference problem inherent in(More)
We demonstrate the design and implementation of a prototype hardware/software architecture for automatic single-word speech recognition on resource-constrained embedded devices. Designed as a voice-activated extension of an existing wireless nurse call system, our prototype device continually listens for a pre-recorded keyword, and uses speech recognition(More)
—We present a heterogeneous system architecture for event-triggered wireless sensing capable of supporting high spatial resolution. The key differentiator between the proposed architecture and alternative state-of-the-art approaches is the ability to simultaneously maximize operational lifetime and minimize end-to-end latency of detected events. Our novel(More)
Resource interference is a fundamental barrier to realizing predictable wireless embedded systems. We address this problem by (<i>i</i>) partitioning application and communication tasks onto dedicated platforms, and (<i>ii</i>) designing a platform interconnect to facilitate asynchronous message exchange with predictable run-time behavior. We motivate the(More)
  • 1