Resve A. Saleh

Learn More
Multiprocessor system-on-chip (MP-SoC) platforms are emerging as an important trend for SoC design. Power and wire design constraints are forcing the adoption of new design methodologies for system-on-chip (SoC), namely, those that incorporate modularity and explicit parallelism. To enable these MP-SoC platforms, researchers have recently pursued scaleable(More)
System on Chip (SOCJ design in theforthcoming billion transisror era will involve the integration of numerous hererogeneous semiconductor intellectual proper@ ( I f ) blocks. Some of the main problems in the ultra deep sub micron technologies characterized by gate lengths in rhe range of 50-100 nm arise from non-scalable global wire delays, failure ro(More)
A novel method for on-line fault detection and location in Network-on-chip (NoC) communication fabrics is introduced. This approach is able to distinguish between faults in the communication links and faults in the NoC switches. The idea is based on the use of code-disjoint routing elements, combined with parity check encoding for the inter-switch links. We(More)
In this paper, we present a novel built-in self-test methodology for testing the inter-switch links of network-on-chip (NoC) based chips. This methodology uses a high-level fault model that accounts for crosstalk effects due to inter-wire coupling. The novelty of our approach lies in the progressive reuse of the NoC infrastructure to transport test data to(More)
404 0740-7475/05/$20.00 © 2005 IEEE Copublished by the IEEE CS and the IEEE CASS IEEE Design & Test of Computers SOC DESIGN in the coming billion-transistor era implies the extensive use and seamless integration of numerous semiconductor IP blocks in the form of processors, embedded memories, and smart interconnects. Such systems will behave like(More)
Recently, the use of multiprocessor system-on-chip (MP-SoC) platforms has emerged as an important integrated circuit design trend for high-performance computing applications. As the number of reusable intellectual property (IP) blocks on such platforms continues to increase, many have argued that monolithic bus-based interconnect architectures will not be(More)
Network-on-chip (NoC) communication fabrics will be increasingly used in many large multicore system-on-chip designs in the near future. A relevant challenge that arises from this trend is that the test costs associated with NoC infrastructures may account for a significant part of the total test budget. In this paper, we present a novel methodology for(More)
System on Chip (SoC) design in the forthcoming billiontransistor era will involve the integration of numerous heterogeneous semiconductor intellectual property (IP) blocks. Some of the main problems in the ultra deep submicron technologies arise from non-scalable global wire delays, failure to achieve global synchronization and difficulties associated with(More)