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In the present era of secret communication, steganography has obtained a significant place in information security by means of offering variety of techniques for cleverly hiding the information. In addition to the existing hardware stego algorithms, an adaptive block hardware stego system has been proposed in this paper which follows a shortest path(More)
Error detection and correction based on double-sampling is used as common technique to handle timing errors while scaling Vdd for energy efficiency. An additional sampling element is inserted in the critical paths of the design, to double sample the outputs of those logic paths at different time instances that may fail while scaling the supply voltage or(More)
Voltage scaling has been used as a prominent technique to improve energy efficiency in digital systems, scaling down supply voltage effects in quadratic reduction in energy consumption of the system. Reducing supply voltage induces timing errors in the system that are corrected through additional error detection and correction circuits. In this paper we are(More)
This paper presents the design and experimental results of a high speed, low-power, thermometer coded and current steered 6-bit digital-to-analog converter (DAC). It is based on a hybrid architecture with a switched current matrix controlled by the four most significant digital bits, and a conventional 2-bit current source controlled by the two least(More)
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