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- Klaus Hering, Reiner Haupt, Thomas Villmann
- Workshop on Parallel and Distributed Simulation
- 1996

The partitioning of complex processor models on the gate and register-transfer level for parallel functional simulation based on the clock-cycle algorithm is considered. We introduce a hierarchical partitioning scheme combining various partitioning algorithms in the frame of a competing strategy. Melting together different partitioning results within one… (More)

Parallelization of VLSI-simulation exploiting model-inherent parallelism is a promising way to accelerate veri¯cation processes for whole processor designs. Thereby partitioning of hardware models in°uences the e±ciency of following parallel simulations essentially. Based on a formal model of Parallel Cycle Simulation we introduce partition valuation… (More)

The functional logic simulation on the basis of the gate{ and register{level plays

- KLAUS HERING, REINER HAUPT
- 1997

Parallelization of logic simulation on register-transfer and gate level is a promising way to accelerate extremely time-extensive system simulation processes during the design of whole processor structures. The background of this paper is given by the functional sim-ulator parallelTEXSIM realizing simulation based on the clock-cycle algorithm over… (More)

- K. Hering, R. Haupt, Th. Villmann
- 1995

The partitioning of complex processor models on the gate and register-transfer level for parallel functional simulation based on the clock-cycle algorithm is considered. We introduce a hierarchical partitioning scheme combining various partitioning algorithms in the frame of a competing strategy. Melting together the di®erent partitioning results within one… (More)

- Reiner Haupt, Klaus Hering, Thomas Siedschlag
- 1998

*564)+6: The application of Evolutionary Algorithms in hierarchical model partitioning for parallel system simulation in VLSI design processes has proven to be successful. Thereby, individuals embody partitions of hardware designs. On the basis of a formal model of parallel cycle simulation a ¯tness function is chosen combining load balancing and… (More)

- Hendrik Schulze, Reiner Haupt, Klaus Hering
- PARCO
- 1999

- Thomas Villmann, Reiner Haupt, Klaus Hering
- IJCNN
- 2000

Parallelization of logic simulation is a promising way to accelerate verification processes for whole processor designs. Partitioning of hardware models influences the efficiency of following parallel simulations essentially. Within the frame of a 2-level hierarchical partitioning scheme Parallel Evolutionary Algorithms are successfully applied using a lazy… (More)

- Th. Villmann, R. Haupt, K. Hering, H. Schulze
- 1999

We introduce a multiple subpopulation approach for parallel evolutionary algorithms the migration scheme of which follows a SOM-like dynamics. We succesfully apply this approach to clustering in both VLSI-design and psychotherapy research. The advantages of the approach are shown which consist in a reduced communication overhead between the sub-populations… (More)

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