Reiner Genevriere

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In this paper a methodology for automatic area minimizing resynthesis of synchronous, digital circuitry was introduced. The circuit is entirely treated as a finite-state machine. The entire procedure works on a symbolic transition system which is represented as a set of BDDs.The redesign task is mainly understood as a re-encoding problem of the switching(More)
Memory is one of the most important components to be optimized in the several phases of the synthesis process. In behavioral synthesis, a memory is viewed as an abstract construct which hides the detail implementations of the memory. Consequently, for a vendor's memory, behavioral synthesis should create a clean model of the memory wrapper which abstracts(More)
  • A V Aho, R Sethi, +7 authors Psf-Paderborn
  • 2002
This paper shows the integration of RT-level advice into our system-level synthesis methodology. A standard C file is analyzed, HW is extracted and synthesized by our high-level synthesis tool PMOSS. For supporting a fast exploration of the design space, the final task of logic synthesis is enabled after a separate estimation phase. In this estimation phase(More)
  • A V Aho, R Sethi, +7 authors Psf-Paderborn
  • 1996
several points within the design space are examined by the involved advice tool. Thus, predictions of the final result can be computed without completely synthesizing the whole design. This leads to a reasonable reduction of design time because only the design with the best estimated characteristics is given to logic synthesis for implementation. Future(More)
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