Reiner Genevriere

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In this paper a methodology for automatic area minimizing resynthesis of synchronous, digital circuitry was introduced. The circuit is entirely treated as a finite-state machine. The entire procedure works on a symbolic transition system which is represented as a set of BDDs.The redesign task is mainly understood as a re-encoding problem of the switching(More)
  • A V Aho, R Sethi, +7 authors Psf-Paderborn
  • 1996
In this paper, the integration of RT-level advice into the system-level synthesis methodology is examined. The synthesis procedure starts from a system-level specification given by standard C code. HW is extracted and synthesized by means of high-level synthesis. The result is a structural VHDL description. In order to shorten the design loop in a(More)
Memory is one of the most important components to be optimized in the several phases of the synthesis process. In behavioral synthesis, a memory is viewed as an abstract construct which hides the detail implementations of the memory. Consequently, for a vendor's memory, behavioral synthesis should create a clean model of the memory wrapper which abstracts(More)
  • A V Aho, R Sethi, +7 authors Psf-Paderborn
  • 2002
In this paper, the integration of RT-level advice into the system-level synthesis methodology is examined. The synthesis procedure starts from a system-level specification given by standard C code. HW is extracted and synthesized by means of high-level synthesis. The result is a structural VHDL description. In order to shorten the design loop in a(More)
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