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High performance approximate adders typically comprise of multiple smaller sub-adders, carry prediction units and error correction units. In this paper, we present a <i>low-latency generic accuracy configurable adder</i> to support variable approximation modes. It provides a higher number of potential configurations compared to state-of-the-art, thus(More)
We present a survey of approximate techniques and discuss concepts for building power-/energy-efficient computing components reaching from approximate accelerators to arithmetic blocks (like adders and multipliers). We provide a systematical understanding of how to generate and explore the design space of approximate components, which enables a wide-range(More)
Aerial video imagery is widely used in mapping, surveillance and monitoring applications. An aerial video can give sufficient information, but it does not offer the freedom and flexibility of working with a geo-registered image or map. Our paper provides a cost effective, robust and efficient solution for real time video registration. We propose a fast(More)
Approximate adders are widely being advocated for developing hardware accelerators to perform complex arithmetic operations. Most of the state-of-the-art accuracy configurable approximate adders utilize some integrated Error Detection and Correction (EDC) circuitry. Consequently, the accumulated area overhead due to the EDC (integrated within individual(More)
Quality system design on dynamic partially reconfigurable platform needs exploration of a vast and multi-dimensional design space for (1) selection among implementation variants of hardware accelerators, (2) partitioning the reconfigurable fabric, and (3) their placement on the reconfigurable fabric partitions. This paper presents a novel methodology ISOMER(More)