Razak Hossain

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This paper describes a new implementation of the ST20-C2 CPU architecture. The design involves an eight-stage pipeline with hardware support to execute up to three instructions in a cycle. Branch prediction is based on a 2-bit predictor scheme with a 1024-entry Branch History Table and a 64 entry Branch Target Buffer and a 4-entry Return Stack. The(More)
Synthesizable processor cores capable of execution speeds typically only achievable by complex custom solutions is important because of the ever-increasing CPU performance levels demanded by modern embedded applications. Another reason is that product design cycles have often decreased to only a few months. In many cases, using lengthy custom design flows(More)
Synthesizable processor cores capable of execution speeds typically only achievable by complex custom solutions is important because of the ever-increasing CPU performance levels demanded by modern embedded applications. Another reason is that product design cycles have often decreased to only a few months. In many cases, using lengthy custom design flows(More)
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